Defined in 1 files as a prototype:
Defined in 1 files as a function:
Referenced in 1 files:
Smatch caller information:
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn20/dcn20_hwseq.c dcn20_program_front_end_for_ctx() -> (struct hwseq_private_funcs)->update_odm()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dc | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->ctx | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->current_state | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->force_pstate_change_control | 0,2796816337411768320 |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->program_det_segments | 0,440092313918779392 |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->program_det_size | 0,3324494803509547008,8166695353123938304 |
| PARAM_VALUE | 0 | dc->res_pool->mpc->funcs->get_mpcc_for_dpp_from_secondary | 0 |
| PARAM_VALUE | 0 | dc->res_pool->mpc->funcs->remove_mpcc_from_secondary | 0 |
| PARAM_VALUE | 0 | dc->res_pool->pipe_count | 1-u32max |
| PARAM_VALUE | 1 | context | 4096-ptr_max |
| PARAM_VALUE | 1 | context->res_ctx.pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 2 | pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 2 | pipe_ctx->prev_odm_pipe | 0 |
| PARAM_VALUE | 2 | pipe_ctx->stream | 1-u64max |
| PARAM_VALUE | 2 | pipe_ctx->top_pipe | 0 |
| PARAM_VALUE | 2 | pipe_ctx->update_flags.bits.odm | 1 |
| CAPPED_DATA | 0 | dc->res_pool->pipe_count | 1 |
| CAPPED_DATA | 1 | context->stream_count | 1 |
| DATA_SOURCE | 0 | dc | $0 |
| DATA_SOURCE | 1 | context | $1 |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn20/dcn20_hwseq.c dcn20_program_pipe() -> (struct hwseq_private_funcs)->update_odm()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dc | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->hwseq | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->force_pstate_change_control | 0,2796816337411768320 |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->program_det_segments | 0,440092313918779392 |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->program_det_size | 0,3324494803509547008,8166695353123938304 |
| PARAM_VALUE | 0 | dc->res_pool->pipe_count | 1-u32max |
| PARAM_VALUE | 0 | dc->res_pool->res_cap->num_dwb | 0-1 |
| PARAM_VALUE | 1 | context | 4096-ptr_max |
| PARAM_VALUE | 1 | context->res_ctx.pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 2 | pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 2 | pipe_ctx->plane_res.dpp->degamma_params.rgb_resulted->delta_blue_reg | 0-4294967295 |
| PARAM_VALUE | 2 | pipe_ctx->plane_res.dpp->degamma_params.rgb_resulted->delta_green_reg | 0-4294967295 |
| PARAM_VALUE | 2 | pipe_ctx->plane_res.dpp->degamma_params.rgb_resulted->delta_red_reg | 0-4294967295 |
| PARAM_VALUE | 2 | pipe_ctx->plane_res.dpp->regamma_params.rgb_resulted->delta_blue_reg | 0-4294967295 |
| PARAM_VALUE | 2 | pipe_ctx->plane_res.dpp->regamma_params.rgb_resulted->delta_green_reg | 0-4294967295 |
| PARAM_VALUE | 2 | pipe_ctx->plane_res.dpp->regamma_params.rgb_resulted->delta_red_reg | 0-4294967295 |
| PARAM_VALUE | 2 | pipe_ctx->plane_res.dpp->shaper_params.rgb_resulted->delta_blue_reg | 0-4294967295 |
| PARAM_VALUE | 2 | pipe_ctx->plane_res.dpp->shaper_params.rgb_resulted->delta_green_reg | 0-4294967295 |
| PARAM_VALUE | 2 | pipe_ctx->plane_res.dpp->shaper_params.rgb_resulted->delta_red_reg | 0-4294967295 |
| PARAM_VALUE | 2 | pipe_ctx->plane_res.hubp->funcs->hubp_wait_pipe_read_start | 0,8092735316039704576 |
| PARAM_VALUE | 2 | pipe_ctx->stream_res.tg->funcs->program_global_sync | 0,4096-ptr_max |
| PARAM_VALUE | 2 | pipe_ctx->stream_res.tg->funcs->set_vtg_params | 0,4096-ptr_max |
| PARAM_VALUE | 2 | pipe_ctx->update_flags.bits.odm | 1 |
| DATA_SOURCE | 0 | dc | $0 |
| DATA_SOURCE | 1 | context | $2 |
| DATA_SOURCE | 2 | pipe_ctx | $1 |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn401/dcn401_hwseq.c dcn401_program_front_end_for_ctx() -> (struct hwseq_private_funcs)->update_odm()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dc | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->current_state | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->debug.enable_block_sequence_programming | 0 |
| PARAM_VALUE | 0 | dc->res_pool | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->force_pstate_change_control | 0,2796816337411768320 |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->program_det_segments | 0,440092313918779392 |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->program_det_size | 0,3324494803509547008,8166695353123938304 |
| PARAM_VALUE | 0 | dc->res_pool->mpc->funcs->get_mpcc_for_dpp_from_secondary | 0 |
| PARAM_VALUE | 0 | dc->res_pool->mpc->funcs->remove_mpcc_from_secondary | 0 |
| PARAM_VALUE | 0 | dc->res_pool->pipe_count | 1-u32max |
| PARAM_VALUE | 1 | context | 4096-ptr_max |
| PARAM_VALUE | 1 | context->res_ctx.pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 2 | pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 2 | pipe_ctx->prev_odm_pipe | 0 |
| PARAM_VALUE | 2 | pipe_ctx->stream | 1-u64max |
| PARAM_VALUE | 2 | pipe_ctx->top_pipe | 0 |
| PARAM_VALUE | 2 | pipe_ctx->update_flags.bits.odm | 1 |
| CAPPED_DATA | 0 | dc->res_pool->pipe_count | 1 |
| CAPPED_DATA | 1 | context->stream_count | 1 |
| DATA_SOURCE | 0 | dc | $0 |
| DATA_SOURCE | 1 | context | $1 |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn401/dcn401_hwseq.c dcn401_program_pipe() -> (struct hwseq_private_funcs)->update_odm()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dc | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->hwseq | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->hubbub | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->force_pstate_change_control | 0,2796816337411768320 |
| PARAM_VALUE | 0 | dc->res_pool->pipe_count | 1-u32max |
| PARAM_VALUE | 1 | context | 4096-ptr_max |
| PARAM_VALUE | 1 | context->res_ctx.pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 2 | pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 2 | pipe_ctx->plane_res.dpp->degamma_params.rgb_resulted->delta_blue_reg | 0-4294967295 |
| PARAM_VALUE | 2 | pipe_ctx->plane_res.dpp->degamma_params.rgb_resulted->delta_green_reg | 0-4294967295 |
| PARAM_VALUE | 2 | pipe_ctx->plane_res.dpp->degamma_params.rgb_resulted->delta_red_reg | 0-4294967295 |
| PARAM_VALUE | 2 | pipe_ctx->plane_res.dpp->regamma_params.rgb_resulted->delta_blue_reg | 0-4294967295 |
| PARAM_VALUE | 2 | pipe_ctx->plane_res.dpp->regamma_params.rgb_resulted->delta_green_reg | 0-4294967295 |
| PARAM_VALUE | 2 | pipe_ctx->plane_res.dpp->regamma_params.rgb_resulted->delta_red_reg | 0-4294967295 |
| PARAM_VALUE | 2 | pipe_ctx->plane_res.dpp->shaper_params.rgb_resulted->delta_blue_reg | 0-4294967295 |
| PARAM_VALUE | 2 | pipe_ctx->plane_res.dpp->shaper_params.rgb_resulted->delta_green_reg | 0-4294967295 |
| PARAM_VALUE | 2 | pipe_ctx->plane_res.dpp->shaper_params.rgb_resulted->delta_red_reg | 0-4294967295 |
| PARAM_VALUE | 2 | pipe_ctx->stream_res.tg->funcs->program_global_sync | 0,4096-ptr_max |
| PARAM_VALUE | 2 | pipe_ctx->stream_res.tg->funcs->set_vtg_params | 0,4096-ptr_max |
| PARAM_VALUE | 2 | pipe_ctx->top_pipe->dml_dlg_sys_param.deepsleep_dcfclk_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 2 | pipe_ctx->top_pipe->dml_dlg_sys_param.mem_trip_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 2 | pipe_ctx->top_pipe->dml_dlg_sys_param.t_extra_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 2 | pipe_ctx->top_pipe->dml_dlg_sys_param.t_mclk_wm_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 2 | pipe_ctx->top_pipe->dml_dlg_sys_param.t_sr_wm_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 2 | pipe_ctx->top_pipe->dml_dlg_sys_param.t_urg_wm_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 2 | pipe_ctx->top_pipe->dml_dlg_sys_param.total_flip_bw | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 2 | pipe_ctx->top_pipe->dml_input.clks_cfg.dcfclk_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 2 | pipe_ctx->top_pipe->dml_input.clks_cfg.dispclk_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 2 | pipe_ctx->top_pipe->dml_input.clks_cfg.dppclk_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 2 | pipe_ctx->top_pipe->dml_input.clks_cfg.refclk_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 2 | pipe_ctx->top_pipe->dml_input.clks_cfg.socclk_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 2 | pipe_ctx->top_pipe->dml_input.dout.output_bpp | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 2 | pipe_ctx->top_pipe->dml_input.dout.wb.wb_hratio | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 2 | pipe_ctx->top_pipe->dml_input.dout.wb.wb_vratio | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 2 | pipe_ctx->top_pipe->dml_input.pipe.dest.pixel_rate_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 2 | pipe_ctx->top_pipe->dml_input.pipe.scale_ratio_depth.hscl_ratio | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 2 | pipe_ctx->top_pipe->dml_input.pipe.scale_ratio_depth.hscl_ratio_c | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 2 | pipe_ctx->top_pipe->dml_input.pipe.scale_ratio_depth.vinit | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 2 | pipe_ctx->top_pipe->dml_input.pipe.scale_ratio_depth.vinit_bot | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 2 | pipe_ctx->top_pipe->dml_input.pipe.scale_ratio_depth.vinit_bot_c | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 2 | pipe_ctx->top_pipe->dml_input.pipe.scale_ratio_depth.vinit_c | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 2 | pipe_ctx->top_pipe->dml_input.pipe.scale_ratio_depth.vscl_ratio | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 2 | pipe_ctx->top_pipe->dml_input.pipe.scale_ratio_depth.vscl_ratio_c | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 2 | pipe_ctx->top_pipe->dml_input.pipe.src.dcc_fraction_of_zs_req_chroma | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 2 | pipe_ctx->top_pipe->dml_input.pipe.src.dcc_fraction_of_zs_req_luma | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 2 | pipe_ctx->top_pipe->dml_input.pipe.src.xfc_params.xfc_tslv_vready_offset_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 2 | pipe_ctx->top_pipe->dml_input.pipe.src.xfc_params.xfc_tslv_vupdate_offset_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 2 | pipe_ctx->top_pipe->dml_input.pipe.src.xfc_params.xfc_tslv_vupdate_width_us | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 2 | pipe_ctx->top_pipe->pipe_dlg_param.pixel_rate_mhz | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 2 | pipe_ctx->top_pipe->top_pipe | 0 |
| PARAM_VALUE | 2 | pipe_ctx->update_flags.bits.odm | 1 |
| DATA_SOURCE | 0 | dc | $0 |
| DATA_SOURCE | 1 | context | $2 |
| DATA_SOURCE | 2 | pipe_ctx | $1 |
| NOCHECK_CALL |