Defined in 1 files as a function:
Referenced in 1 files:
Smatch caller information:
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn50/dcn50_hwseq.c dcn50_initialize_min_clocks() -> (struct clk_mgr_funcs)->update_clocks()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | clk_mgr_base | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->bw_params | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->bw_params->clk_table.entries | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz | 10000 |
| PARAM_VALUE | 1 | context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support | 1 |
| PARAM_VALUE | 1 | context->bw_ctx.bw.dcn.clk.p_state_change_support | 1 |
| PARAM_VALUE | 2 | safe_to_lower | 1 |
| CONTAINER | 0 | *(-0-8+0) | $(-1) |
| CONTAINER | 1 | *(-0-8-1960+1880) | $(-1) |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn21/dcn21_hwseq.c dcn21_exit_optimized_pwr_state() -> (struct clk_mgr_funcs)->update_clocks()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | clk_mgr_base | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->funcs->is_dc_mode_present | 0,4166653776963936256 |
| PARAM_VALUE | 1 | *context->res_ctx.link_enc_cfg_ctx.link_enc_avail | s32min-s32max |
| PARAM_VALUE | 2 | safe_to_lower | 0 |
| DATA_SOURCE | 1 | context | $1 |
| CONTAINER | 0 | *(-0-8+0) | $(-1) |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HALF_LOCKED2 | _T->lock |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn21/dcn21_hwseq.c dcn21_optimize_pwr_state() -> (struct clk_mgr_funcs)->update_clocks()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | clk_mgr_base | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->funcs->is_dc_mode_present | 0,4166653776963936256 |
| PARAM_VALUE | 1 | *context->res_ctx.link_enc_cfg_ctx.link_enc_avail | s32min-s32max |
| PARAM_VALUE | 2 | safe_to_lower | 1 |
| DATA_SOURCE | 1 | context | $1 |
| CONTAINER | 0 | *(-0-8+0) | $(-1) |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HALF_LOCKED2 | _T->lock |
drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_dpms.c enable_link_dp() -> (struct clk_mgr_funcs)->update_clocks()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | clk_mgr_base | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | context | 4096-ptr_max |
| PARAM_VALUE | 1 | context->clk_mgr | 4096-ptr_max |
| PARAM_VALUE | 1 | context->clk_mgr->funcs | 4096-ptr_max |
| PARAM_VALUE | 2 | safe_to_lower | 0 |
| CAPPED_DATA | 1 | context->stream_count | 1 |
| DATA_SOURCE | 1 | context | $0 |
| CONTAINER | 0 | *(-0-8+0) | $(-1) |
| CONTAINER | 1 | -0-8-39456+0 | $(-1) |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn10/dcn10_hwseq.c dcn10_optimize_bandwidth() -> (struct clk_mgr_funcs)->update_clocks()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | clk_mgr_base | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | context | 4096-ptr_max |
| PARAM_VALUE | 2 | safe_to_lower | 1 |
| DATA_SOURCE | 1 | context | $1 |
| CONTAINER | 0 | *(-0-8+0) | $(-1) |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn10/dcn10_hwseq.c dcn10_prepare_bandwidth() -> (struct clk_mgr_funcs)->update_clocks()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | clk_mgr_base | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | context | 4096-ptr_max |
| PARAM_VALUE | 2 | safe_to_lower | 0 |
| DATA_SOURCE | 1 | context | $1 |
| CONTAINER | 0 | *(-0-8+0) | $(-1) |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn10/dcn10_hwseq.c dcn10_set_clock() -> (struct clk_mgr_funcs)->update_clocks()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | clk_mgr_base | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->funcs->get_clock | 1185672433473220608 |
| PARAM_VALUE | 0 | clk_mgr_base->funcs->update_clocks | 4096-ptr_max |
| PARAM_VALUE | 2 | safe_to_lower | 1 |
| CONTAINER | 0 | *(-0-8+0) | $(-1) |
| CONTAINER | 1 | *(-0-8-1960+1880) | $(-1) |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn20/dcn20_hwseq.c dcn20_optimize_bandwidth() -> (struct clk_mgr_funcs)->update_clocks()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | clk_mgr_base | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | context | 4096-ptr_max |
| PARAM_VALUE | 2 | safe_to_lower | 1 |
| BUF_SIZE | 1 | context | (-1),370336 |
| BUF_SIZE | 1 | context | (-1),370336 |
| DATA_SOURCE | 1 | context | $1 |
| CONTAINER | 0 | *(-0-8+0) | $(-1) |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn20/dcn20_hwseq.c dcn20_prepare_bandwidth() -> (struct clk_mgr_funcs)->update_clocks()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | clk_mgr_base | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | context | 4096-ptr_max |
| PARAM_VALUE | 2 | safe_to_lower | 0 |
| DATA_SOURCE | 1 | context | $1 |
| CONTAINER | 0 | *(-0-8+0) | $(-1) |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dce110/dce110_hwseq.c dce110_optimize_bandwidth() -> (struct clk_mgr_funcs)->update_clocks()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | clk_mgr_base | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | context | 4096-ptr_max |
| PARAM_VALUE | 2 | safe_to_lower | 1 |
| DATA_SOURCE | 1 | context | $1 |
| CONTAINER | 0 | -0-8+0 | $(-1) |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dce110/dce110_hwseq.c dce110_prepare_bandwidth() -> (struct clk_mgr_funcs)->update_clocks()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | clk_mgr_base | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | context | 4096-ptr_max |
| PARAM_VALUE | 2 | safe_to_lower | 0 |
| DATA_SOURCE | 1 | context | $1 |
| CONTAINER | 0 | -0-8+0 | $(-1) |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_helpers.c dm_helpers_dp_handle_test_pattern_request() -> (struct clk_mgr_funcs)->update_clocks()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | clk_mgr_base | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->bw_params | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | context | 4096-ptr_max |
| PARAM_VALUE | 1 | context->bw_ctx.bw.dcn.clk.p_state_change_support | 0 |
| PARAM_VALUE | 2 | safe_to_lower | 0 |
| CONTAINER | 0 | *(-0-8+0) | $(-1) |
| CONTAINER | 1 | *(-0-8-1960+1880) | $(-1) |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HALF_LOCKED2 | &aconnector->hpd_lock | ||
| HALF_LOCKED2 | &adev->dm.dc_lock |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn401/dcn401_hwseq.c dcn401_hardware_release() -> (struct clk_mgr_funcs)->update_clocks()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | clk_mgr_base | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | context | 4096-ptr_max |
| PARAM_VALUE | 1 | context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down | 1 |
| PARAM_VALUE | 1 | context->bw_ctx.bw.dcn.clk.p_state_change_support | 1 |
| PARAM_VALUE | 2 | safe_to_lower | 1 |
| CONTAINER | 0 | *(-0-8+0) | $(-1) |
| CONTAINER | 1 | *(-0-8-1960+1880) | $(-1) |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn401/dcn401_hwseq.c dcn401_hardware_release() -> (struct clk_mgr_funcs)->update_clocks()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | clk_mgr_base | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->clks.p_state_change_support | 0 |
| PARAM_VALUE | 0 | clk_mgr_base->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | context | 4096-ptr_max |
| PARAM_VALUE | 1 | context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down | 1 |
| PARAM_VALUE | 2 | safe_to_lower | 1 |
| CONTAINER | 0 | *(-0-8+0) | $(-1) |
| CONTAINER | 1 | *(-0-8-1960+1880) | $(-1) |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn401/dcn401_hwseq.c dcn401_initialize_min_clocks() -> (struct clk_mgr_funcs)->update_clocks()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | clk_mgr_base | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->bw_params | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->bw_params->clk_table.entries | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->funcs->get_dispclk_from_dentist | 0,2073416932931796992,2887665452536954880,7941745217211535360 |
| PARAM_VALUE | 1 | context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz | 10000 |
| PARAM_VALUE | 1 | context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support | 1 |
| PARAM_VALUE | 1 | context->bw_ctx.bw.dcn.clk.p_state_change_support | 1 |
| PARAM_VALUE | 2 | safe_to_lower | 1 |
| CONTAINER | 0 | *(-0-8+0) | $(-1) |
| CONTAINER | 1 | *(-0-8-1960+1880) | $(-1) |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn401/dcn401_hwseq.c dcn401_optimize_bandwidth() -> (struct clk_mgr_funcs)->update_clocks()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | clk_mgr_base | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | context | 4096-ptr_max |
| PARAM_VALUE | 2 | safe_to_lower | 1 |
| BUF_SIZE | 1 | context | (-1),370336 |
| BUF_SIZE | 1 | context | (-1),370336 |
| DATA_SOURCE | 1 | context | $1 |
| CONTAINER | 0 | *(-0-8+0) | $(-1) |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn401/dcn401_hwseq.c dcn401_prepare_bandwidth() -> (struct clk_mgr_funcs)->update_clocks()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | clk_mgr_base | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | context | 4096-ptr_max |
| PARAM_VALUE | 1 | context->bw_ctx.bw.dcn.clk.p_state_change_support | 0 |
| PARAM_VALUE | 2 | safe_to_lower | 0 |
| DATA_SOURCE | 1 | context | $1 |
| CONTAINER | 0 | *(-0-8+0) | $(-1) |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dce100/dce100_hwseq.c dce100_optimize_bandwidth() -> (struct clk_mgr_funcs)->update_clocks()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | clk_mgr_base | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | context | 4096-ptr_max |
| PARAM_VALUE | 2 | safe_to_lower | 1 |
| DATA_SOURCE | 1 | context | $1 |
| CONTAINER | 0 | *(-0-8+0) | $(-1) |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dce100/dce100_hwseq.c dce100_prepare_bandwidth() -> (struct clk_mgr_funcs)->update_clocks()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | clk_mgr_base | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | context | 4096-ptr_max |
| PARAM_VALUE | 2 | safe_to_lower | 0 |
| DATA_SOURCE | 1 | context | $1 |
| CONTAINER | 0 | *(-0-8+0) | $(-1) |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn32/dcn32_hwseq.c dcn32_initialize_min_clocks() -> (struct clk_mgr_funcs)->update_clocks()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | clk_mgr_base | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->bw_params | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->bw_params->clk_table.entries | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | clk_mgr_base->funcs->get_dispclk_from_dentist | 0,2073416932931796992,2887665452536954880,7941745217211535360 |
| PARAM_VALUE | 0 | clk_mgr_base->funcs->update_clocks | 4096-ptr_max |
| PARAM_VALUE | 1 | context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz | 10000 |
| PARAM_VALUE | 1 | context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support | 1 |
| PARAM_VALUE | 1 | context->bw_ctx.bw.dcn.clk.p_state_change_support | 1 |
| PARAM_VALUE | 2 | safe_to_lower | 1 |
| CONTAINER | 0 | *(-0-8+0) | $(-1) |
| CONTAINER | 1 | *(-0-8-1960+1880) | $(-1) |
| NOCHECK_CALL |