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Documented in 1 files:

Defined in 1 files as a function:

Referenced in 1 files:

Smatch caller information:

drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce120/dce120_clk_mgr.c dce121_clk_mgr_construct() -> dce121_clock_patch_xgmi_ss_info()

Type Parameter Key Value
PARAM_VALUE 0 clk_mgr_dce 4096-ptr_max
PARAM_VALUE 0 clk_mgr_dce->base.clks.max_supported_dispclk_khz 600000,625000,643000,1132000,1133000
PARAM_VALUE 0 clk_mgr_dce->base.ctx 4096-ptr_max
PARAM_VALUE 0 clk_mgr_dce->base.ctx->asic_id.chip_id 0-u16max
PARAM_VALUE 0 clk_mgr_dce->base.ctx->asic_id.pci_revision_id 0-255
PARAM_VALUE 0 clk_mgr_dce->base.ctx->clk_reg_offsets 4096-ptr_max
PARAM_VALUE 0 clk_mgr_dce->base.ctx->created_bios 1
PARAM_VALUE 0 clk_mgr_dce->base.ctx->dc 4096-ptr_max
PARAM_VALUE 0 clk_mgr_dce->base.ctx->dc_bios 4096-ptr_max
PARAM_VALUE 0 clk_mgr_dce->base.ctx->dc_sink_id_count 0
PARAM_VALUE 0 clk_mgr_dce->base.ctx->dc_stream_id_count 0
PARAM_VALUE 0 clk_mgr_dce->base.ctx->dce_version 0-11,13-33
PARAM_VALUE 0 clk_mgr_dce->base.ctx->dcn_reg_offsets 4096-ptr_max
PARAM_VALUE 0 clk_mgr_dce->base.ctx->driver_context 4096-ptr_max
PARAM_VALUE 0 clk_mgr_dce->base.ctx->gpio_service 4096-ptr_max
PARAM_VALUE 0 clk_mgr_dce->base.ctx->logger 4096-ptr_max
PARAM_VALUE 0 clk_mgr_dce->base.ctx->nbio_reg_offsets 4096-ptr_max
PARAM_VALUE 0 clk_mgr_dce->base.ctx->perf_trace 4096-ptr_max
PARAM_VALUE 0 clk_mgr_dce->base.dentist_vco_freq_khz s32min-(-1),1-s32max
PARAM_VALUE 0 clk_mgr_dce->base.dprefclk_khz 625000
PARAM_VALUE 0 clk_mgr_dce->base.funcs 4825842539332587520
PARAM_VALUE 0 clk_mgr_dce->base.funcs->dump_clk_registers 0
PARAM_VALUE 0 clk_mgr_dce->base.funcs->enable_pme_wa 0
PARAM_VALUE 0 clk_mgr_dce->base.funcs->execute_clk_mgr_block_sequence 0,6926659037936484352
PARAM_VALUE 0 clk_mgr_dce->base.funcs->get_clock 0
PARAM_VALUE 0 clk_mgr_dce->base.funcs->get_dp_ref_clk_frequency 2412846210009993216
PARAM_VALUE 0 clk_mgr_dce->base.funcs->get_hard_min_fclk 0
PARAM_VALUE 0 clk_mgr_dce->base.funcs->get_max_clock_khz 0
PARAM_VALUE 0 clk_mgr_dce->base.funcs->init_clocks 0
PARAM_VALUE 0 clk_mgr_dce->base.funcs->is_dc_mode_present 0
PARAM_VALUE 0 clk_mgr_dce->base.funcs->is_ips_supported 0
PARAM_VALUE 0 clk_mgr_dce->base.funcs->is_smu_present 0
PARAM_VALUE 0 clk_mgr_dce->base.funcs->notify_wm_ranges 0
PARAM_VALUE 0 clk_mgr_dce->base.funcs->set_max_memclk 0
PARAM_VALUE 0 clk_mgr_dce->base.funcs->set_min_memclk 0
PARAM_VALUE 0 clk_mgr_dce->base.funcs->update_clocks 7021307524348416000
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_mask 3905573408915587072
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_mask->CLK0_ALLOW_DS 0
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_mask->CLK0_BYPASS_SEL 0
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_mask->CLK0_DS_DIV_ID 0
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_mask->CLK1_ALLOW_DS 0
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_mask->CLK1_BYPASS_SEL 0
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_mask->CLK1_DS_DIV_ID 0
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_mask->CLK2_ALLOW_DS 0
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_mask->CLK2_BYPASS_SEL 0
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_mask->CLK2_DS_DIV_ID 0
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_mask->CLK3_ALLOW_DS 0
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_mask->CLK3_BYPASS_SEL 0
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_mask->CLK3_DS_DIV_ID 0
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_mask->CLK4_ALLOW_DS 0
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_mask->CLK4_BYPASS_SEL 0
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_mask->CLK4_DS_DIV_ID 0
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_mask->DENTIST_DPREFCLK_WDIVIDER 2130706432
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_mask->DPREFCLK_SRC_SEL 7
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_mask->FbMult_frac 0
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_mask->FbMult_int 0
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_mask->TIMER_THRESHOLD 0
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_shift 6908719398200115200
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_shift->CLK0_ALLOW_DS 0
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_shift->CLK0_BYPASS_SEL 0
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_shift->CLK0_DS_DIV_ID 0
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_shift->CLK1_ALLOW_DS 0
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_shift->CLK1_BYPASS_SEL 0
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_shift->CLK1_DS_DIV_ID 0
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_shift->CLK2_ALLOW_DS 0
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_shift->CLK2_BYPASS_SEL 0
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_shift->CLK2_DS_DIV_ID 0
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_shift->CLK3_ALLOW_DS 0
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_shift->CLK3_BYPASS_SEL 0
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_shift->CLK3_DS_DIV_ID 0
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_shift->CLK4_ALLOW_DS 0
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_shift->CLK4_BYPASS_SEL 0
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_shift->CLK4_DS_DIV_ID 0
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_shift->DENTIST_DPREFCLK_WDIVIDER 24
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_shift->FbMult_frac 0
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_shift->FbMult_int 0
PARAM_VALUE 0 clk_mgr_dce->clk_mgr_shift->TIMER_THRESHOLD 0
PARAM_VALUE 0 clk_mgr_dce->dfs_bypass_disp_clk 0
PARAM_VALUE 0 clk_mgr_dce->dfs_bypass_enabled 1
PARAM_VALUE 0 clk_mgr_dce->dprefclk_ss_divider 0,100,1000
PARAM_VALUE 0 clk_mgr_dce->regs 5816523318219726848
PARAM_VALUE 0 clk_mgr_dce->regs->CLK0_CLK0_DFS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK0_CLK1_DFS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK0_CLK2_DFS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK0_CLK3_DFS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK0_CLK4_DFS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK0_CLK_PLL_REQ 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK1_CLK0_ALLOW_DS 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK1_CLK0_BYPASS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK1_CLK0_CURRENT_CNT 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK1_CLK0_DFS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK1_CLK0_DS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK1_CLK1_ALLOW_DS 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK1_CLK1_BYPASS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK1_CLK1_CURRENT_CNT 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK1_CLK1_DFS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK1_CLK1_DS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK1_CLK2_ALLOW_DS 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK1_CLK2_BYPASS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK1_CLK2_CURRENT_CNT 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK1_CLK2_DFS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK1_CLK2_DS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK1_CLK3_ALLOW_DS 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK1_CLK3_BYPASS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK1_CLK3_CURRENT_CNT 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK1_CLK3_DFS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK1_CLK3_DS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK1_CLK4_ALLOW_DS 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK1_CLK4_BYPASS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK1_CLK4_CURRENT_CNT 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK1_CLK4_DFS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK1_CLK4_DS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK1_CLK5_ALLOW_DS 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK1_CLK5_BYPASS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK1_CLK5_CURRENT_CNT 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK1_CLK5_DFS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK1_CLK5_DS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK1_CLK_PLL_REQ 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK2_CLK2_DFS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK3_CLK2_DFS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK3_CLK_PLL_REQ 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK4_CLK0_CURRENT_CNT 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK4_CLK2_CURRENT_CNT 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK4_CLK_PLL_REQ 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK5_CLK0_BYPASS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK5_CLK0_CURRENT_CNT 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK5_CLK0_DS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK5_CLK1_BYPASS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK5_CLK1_CURRENT_CNT 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK5_CLK1_DS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK5_CLK2_BYPASS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK5_CLK2_CURRENT_CNT 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK5_CLK2_DS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK5_CLK3_BYPASS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK5_CLK3_CURRENT_CNT 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK5_CLK3_DS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK5_CLK4_BYPASS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK5_CLK4_CURRENT_CNT 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK5_CLK4_DS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK5_spll_field_8 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK6_spll_field_8 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK8_CLK0_BYPASS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK8_CLK0_CURRENT_CNT 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK8_CLK0_DS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK8_CLK1_BYPASS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK8_CLK1_CURRENT_CNT 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK8_CLK1_DS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK8_CLK2_BYPASS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK8_CLK2_CURRENT_CNT 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK8_CLK2_DS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK8_CLK3_BYPASS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK8_CLK3_CURRENT_CNT 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK8_CLK3_DS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK8_CLK4_BYPASS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK8_CLK4_CURRENT_CNT 0
PARAM_VALUE 0 clk_mgr_dce->regs->CLK8_CLK4_DS_CNTL 0
PARAM_VALUE 0 clk_mgr_dce->regs->DENTIST_DISPCLK_CNTL 292
PARAM_VALUE 0 clk_mgr_dce->regs->DPREFCLK_CNTL 280
BUF_SIZE 0 clk_mgr_dce 512
BUF_SIZE 0 clk_mgr_dce 512
DATA_SOURCE 0 clk_mgr_dce $1
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL