| PARAM_VALUE |
0 |
pool |
4096-ptr_max |
| PARAM_VALUE |
0 |
pool->base.clk_src_count |
2-3 |
| PARAM_VALUE |
0 |
pool->base.clock_sources |
4096-ptr_max |
| PARAM_VALUE |
0 |
pool->base.dmcu->funcs |
0,1124573331587444736,1509690769609875456,3807071523771912192,4526291678565003264,5186199206157615104 |
| PARAM_VALUE |
0 |
pool->base.dp_clock_source |
0,4096-ptr_max |
| PARAM_VALUE |
0 |
pool->base.dp_clock_source->dp_clk_src |
1 |
| PARAM_VALUE |
0 |
pool->base.funcs |
6102864332599910400 |
| PARAM_VALUE |
0 |
pool->base.irqs->funcs->to_dal_irq_source |
4096-ptr_max |
| PARAM_VALUE |
0 |
pool->base.irqs->info->ack_mask |
0-1,16,64,256,65536,1048576 |
| PARAM_VALUE |
0 |
pool->base.irqs->info->ack_value |
0-1,16,64,256,65536,1048576 |
| PARAM_VALUE |
0 |
pool->base.irqs->info->enable_mask |
0-1,16,64,256,4096,65536,16777216 |
| PARAM_VALUE |
0 |
pool->base.irqs->info->src_id |
0,19-24 |
| PARAM_VALUE |
0 |
pool->base.res_cap |
3473596689307496448 |
| PARAM_VALUE |
0 |
pool->base.res_cap->num_analog_stream_encoder |
0-1 |
| PARAM_VALUE |
0 |
pool->base.res_cap->num_audio |
2-7 |
| PARAM_VALUE |
0 |
pool->base.res_cap->num_ddc |
6 |
| PARAM_VALUE |
0 |
pool->base.res_cap->num_hpo_dp_link_encoder |
0,2,4 |
| PARAM_VALUE |
0 |
pool->base.res_cap->num_hpo_dp_stream_encoder |
0,3-4 |
| PARAM_VALUE |
0 |
pool->base.res_cap->num_hpo_frl |
0-1 |
| PARAM_VALUE |
0 |
pool->base.res_cap->num_mpc_3dlut |
0-4 |
| PARAM_VALUE |
0 |
pool->base.res_cap->num_stream_encoder |
2-7 |
| PARAM_VALUE |
0 |
pool->base.res_cap->num_timing_generator |
6 |
| PARAM_VALUE |
0 |
pool->base.underlay_pipe_index |
u32max |
| BUF_SIZE |
0 |
pool |
1344 |
| BUF_SIZE |
0 |
pool |
1344 |
| BUF_SIZE |
0 |
pool->base.abm |
(-1),24 |
| BUF_SIZE |
0 |
pool->base.dmcu |
(-1),48 |
| BUF_SIZE |
0 |
pool->base.dp_clock_source |
(-1),24 |
| BUF_SIZE |
0 |
pool->base.funcs |
320 |
| BUF_SIZE |
0 |
pool->base.irqs |
(-1),24 |
| BUF_SIZE |
0 |
pool->base.res_cap |
84 |
| DATA_SOURCE |
0 |
pool |
$2 |
| FUZZY_MAX |
0 |
pool->base.clk_src_count |
3 |
| BIT_INFO |
0 |
pool->base.clk_src_count |
0x2,0x3 |
| HARD_MAX |
0 |
pool->base.clk_src_count |
3 |
| RX_PATH |
|
|
|
| TASK_NOT_RUNNING |
|
|
|
| NOCHECK_CALL |
|
|
|
| NO_OVERFLOW_SIMPLE |
0 |
pool->base.dp_clock_source->dp_ss_params_cnt |
|
| NO_OVERFLOW_SIMPLE |
0 |
pool->base.dp_clock_source->dvi_ss_params_cnt |
|
| NO_OVERFLOW_SIMPLE |
0 |
pool->base.dp_clock_source->hdmi_ss_params_cnt |
|
| NO_OVERFLOW_SIMPLE |
0 |
pool->base.dp_clock_source->lvds_ss_params_cnt |
|