Documented in 1 files:
Defined in 1 files as a prototype:
Defined in 1 files as a function:
Referenced in 5 files:
- drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c, line 141
- drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c, line 3609
- drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c, line 272
- drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c, line 431
- drivers/gpu/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c, line 53
Smatch caller information:
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_surface.c dc_plane_force_dcc_and_tiling_disable() -> (struct hw_sequencer_funcs)->clear_surface_dcc_and_tiling()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 1 | plane_state | 4096-ptr_max |
| PARAM_VALUE | 1 | plane_state->ctx | 4096-ptr_max |
| PARAM_VALUE | 1 | plane_state->ctx->dc | 4096-ptr_max |
| PARAM_VALUE | 1 | plane_state->ctx->dc->current_state | 1-u64max |
| PARAM_VALUE | 1 | plane_state->ctx->dc->current_state->res_ctx.pipe_ctx | 4096-ptr_max |
| PARAM_VALUE | 1 | plane_state->ctx->dc->res_pool | 4096-ptr_max |
| PARAM_VALUE | 1 | plane_state->ctx->dc->res_pool->pipe_count | 1-u32max |
| DATA_SOURCE | 1 | plane_state | $0 |
| DATA_SOURCE | 2 | clear_tiling | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HALF_LOCKED2 | &(plane->dev)->mode_config.panic_lock | ||
| HALF_LOCKED2 | flags |