Defined in 1 files as a prototype:
Defined in 1 files as a function:
Referenced in 2 files:
- drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
- drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c, line 347
Smatch caller information:
drivers/gpu/drm/amd/amdgpu/../display/dc/dccg/dcn401/dcn401_dccg.c dccg401_set_dp_dto() -> dccg401_set_dtbclk_p_src()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dccg | 4096-ptr_max |
| PARAM_VALUE | 0 | dccg->funcs | 4096-ptr_max |
| PARAM_VALUE | 1 | src | 1-2 |
| DATA_SOURCE | 0 | dccg | $0 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn20/dcn20_hwseq.c dcn20_enable_stream_timing() -> (struct dccg_funcs)->set_dtbclk_p_src()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dccg | 4096-ptr_max |
| PARAM_VALUE | 0 | dccg->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | dccg->funcs->set_dtbclk_p_src | 164379742607855616,963594910843088896,2241994770053472256,2682822004430630912,4094372161307451392 |
| PARAM_VALUE | 1 | src | 1 |
| CONTAINER | 0 | -288-8+0 | $(-1) |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn401/dcn401_hwseq.c dcn401_enable_stream_timing() -> (struct dccg_funcs)->set_dtbclk_p_src()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dccg | 4096-ptr_max |
| PARAM_VALUE | 0 | dccg->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | dccg->funcs->set_dtbclk_p_src | 164379742607855616,963594910843088896,2241994770053472256,2682822004430630912,4094372161307451392 |
| PARAM_VALUE | 0 | dccg->funcs->set_pixel_rate_div | 0,960385507676274688,3545156886609068032,5703866155886583808,5992550597655154688,7657711864276148224 |
| PARAM_VALUE | 1 | src | 2 |
| CONTAINER | 0 | *(-288-8+0) | $(-1) |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn401/dcn401_hwseq.c dcn401_enable_stream_timing() -> (struct dccg_funcs)->set_dtbclk_p_src()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dccg | 4096-ptr_max |
| PARAM_VALUE | 0 | dccg->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | dccg->funcs->set_dtbclk_p_src | 164379742607855616,963594910843088896,2241994770053472256,2682822004430630912,4094372161307451392 |
| PARAM_VALUE | 0 | dccg->funcs->set_pixel_rate_div | 0,960385507676274688,3545156886609068032,5703866155886583808,5992550597655154688,7657711864276148224 |
| PARAM_VALUE | 1 | src | 1 |
| CONTAINER | 0 | *(-288-8+0) | $(-1) |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn401/dcn401_hwseq.c dcn401_reset_back_end_for_pipe() -> (struct dccg_funcs)->set_dtbclk_p_src()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dccg | 4096-ptr_max |
| PARAM_VALUE | 0 | dccg->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | dccg->funcs->set_dtbclk_p_src | 164379742607855616,963594910843088896,2241994770053472256,2682822004430630912,4094372161307451392 |
| PARAM_VALUE | 1 | src | 0 |
| CONTAINER | 0 | *(-288-8+0) | $(-1) |
| NOCHECK_CALL |