Defined in 1 files as a prototype:
Defined in 1 files as a function:
Referenced in 2 files:
- drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c, line 926
- drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c, line 383
Smatch caller information:
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn50/dcn50_hwseq.c dcn50_update_dchubp_dpp() -> (struct dccg_funcs)->update_dpp_dto()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dccg | 4096-ptr_max |
| PARAM_VALUE | 0 | dccg->funcs | 4096-ptr_max |
| CONTAINER | 0 | -0-8+0 | $(-1) |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c dcn35_update_clocks_update_dpp_dto() -> (struct dccg_funcs)->update_dpp_dto()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dccg | 4096-ptr_max |
| PARAM_VALUE | 0 | dccg->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | dccg->pipe_dppclk_khz | 4096-ptr_max |
| CONTAINER | 0 | *(-0-8+0) | $(-1) |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c dcn35_update_clocks_update_dpp_dto() -> (struct dccg_funcs)->update_dpp_dto()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dccg | 4096-ptr_max |
| PARAM_VALUE | 0 | dccg->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | *dccg->pipe_dppclk_khz | s32min-s32max |
| PARAM_VALUE | 2 | req_dppclk | 0 |
| CONTAINER | 0 | *(-0-8+0) | $(-1) |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c dcn401_update_clocks_update_dpp_dto() -> (struct dccg_funcs)->update_dpp_dto()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dccg | 4096-ptr_max |
| PARAM_VALUE | 0 | dccg->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | dccg->pipe_dppclk_khz | 4096-ptr_max |
| CONTAINER | 0 | *(-0-8+0) | $(-1) |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c dcn20_update_clocks_update_dpp_dto() -> (struct dccg_funcs)->update_dpp_dto()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dccg | 4096-ptr_max |
| PARAM_VALUE | 0 | dccg->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | dccg->pipe_dppclk_khz | 4096-ptr_max |
| CAPPED_DATA | 1 | dpp_inst | 1 |
| CONTAINER | 0 | *(-0-8+0) | $(-1) |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c dcn32_update_clocks_update_dpp_dto() -> (struct dccg_funcs)->update_dpp_dto()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dccg | 4096-ptr_max |
| PARAM_VALUE | 0 | dccg->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | dccg->pipe_dppclk_khz | 4096-ptr_max |
| CONTAINER | 0 | *(-0-8+0) | $(-1) |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn10/dcn10_hwseq.c dcn10_update_dchubp_dpp() -> (struct dccg_funcs)->update_dpp_dto()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dccg | 4096-ptr_max |
| PARAM_VALUE | 0 | dccg->funcs | 4096-ptr_max |
| CONTAINER | 0 | *(-0-8+0) | $(-1) |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c dcn60_update_clocks_update_dpp_dto() -> (struct dccg_funcs)->update_dpp_dto()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dccg | 4096-ptr_max |
| PARAM_VALUE | 0 | dccg->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | dccg->pipe_dppclk_khz | 4096-ptr_max |
| CONTAINER | 0 | *(-0-8+0) | $(-1) |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c dcn42_update_clocks_update_dpp_dto() -> (struct dccg_funcs)->update_dpp_dto()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dccg | 4096-ptr_max |
| PARAM_VALUE | 0 | dccg->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | dccg->pipe_dppclk_khz | 4096-ptr_max |
| CONTAINER | 0 | *(-0-8+0) | $(-1) |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c dcn42_update_clocks_update_dpp_dto() -> (struct dccg_funcs)->update_dpp_dto()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dccg | 4096-ptr_max |
| PARAM_VALUE | 0 | dccg->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | *dccg->pipe_dppclk_khz | s32min-s32max |
| PARAM_VALUE | 2 | req_dppclk | 0 |
| CONTAINER | 0 | *(-0-8+0) | $(-1) |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21/rn_clk_mgr.c rn_update_clocks_update_dpp_dto() -> (struct dccg_funcs)->update_dpp_dto()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dccg | 4096-ptr_max |
| PARAM_VALUE | 0 | dccg->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | dccg->pipe_dppclk_khz | 4096-ptr_max |
| CONTAINER | 0 | *(-0-8+0) | $(-1) |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_hw_sequencer.c hwss_dccg_update_dpp_dto() -> (struct dccg_funcs)->update_dpp_dto()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dccg | 4096-ptr_max |
| PARAM_VALUE | 0 | dccg->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | dccg->funcs->update_dpp_dto | 2522833544213745664,3051716910004518912,3785366512309571584,4924157768386543616,5635593336178900992,6259980274709327872,9126879307728039936 |
| CONTAINER | 0 | -0-8+0 | $(-1) |
| NOCHECK_CALL |