dc_state_release identifier - Linux source code next-20260811

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linux

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FIXME
- FIXME
  - next-20260811

Defined in 1 files as a prototype:

drivers/gpu/drm/amd/display/dc/dc_state.h, line 39 (as a prototype)

Defined in 1 files as a function:

drivers/gpu/drm/amd/display/dc/core/dc_state.c, line 404 (as a function)

Referenced in 4 files:

Smatch caller information:

drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_connector.c dm_validate_stream_and_context() -> dc_state_release()

Type	Parameter	Key	Value
PARAM_VALUE	0	state	4096-ptr_max
PARAM_VALUE	0	state->bw_ctx.dml.soc.dispclk_dppclk_vco_speed_mhz	-1.797693e+308-1.797693e+308
PARAM_VALUE	0	state->bw_ctx.dml2->architecture	0-4294967295
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ip.config_return_buffer_segment_size_in_kbytes	0-4294967295
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.project	0-4294967295
PARAM_VALUE	0	state->bw_ctx.dml2->v20.scratch.build_synthetic_socbb_params.in_states->num_states	0-4294967295
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->architecture	0-4294967295
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.project	0-4294967295
PARAM_VALUE	0	state->power_source	0
PARAM_VALUE	0	state->refcount.refcount.refs.counter	1
PARAM_VALUE	0	state->res_ctx.link_enc_cfg_ctx.mode	0
PARAM_VALUE	0	*state->res_ctx.link_enc_cfg_ctx.link_enc_avail	(-1)-4
BUF_SIZE	0	state	381336
BUF_SIZE	0	state	381336
DATA_SOURCE	0	state	r dc_state_create
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL

drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c commit_minimal_transition_based_on_current_context() -> dc_state_release()

Type	Parameter	Key	Value
PARAM_VALUE	0	state	4096-ptr_max
NOCHECK_CALL

drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c commit_minimal_transition_state() -> dc_state_release()

Type	Parameter	Key	Value
PARAM_VALUE	0	state	4096-ptr_max
PARAM_VALUE	0	state->res_ctx.pipe_ctx	4096-ptr_max
BUF_SIZE	0	state	(-1),370336
BUF_SIZE	0	state	(-1),370336
CAPPED_DATA	0	state	1
DATA_SOURCE	0	state	$1
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
LOCK2		&dm->dc_lock
HALF_LOCKED2		&adev->reset_domain->sem
HALF_LOCKED2		&of->mutex
HALF_LOCKED2		&pool->lock
HALF_LOCKED2		global &drm_unplug_srcu
TYPE_LOCK		(struct amdgpu_display_manager)->dc_lock

drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c copy_stream_update_to_stream() -> dc_state_release()

Type	Parameter	Key	Value
PARAM_VALUE	0	state	4096-ptr_max
PARAM_VALUE	0	state->bw_ctx.dml.ip.dcfclk_cstate_latency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.dispclk_ramp_margin_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.dsc_delay_factor_wa	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.max_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.max_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.min_prefetch_in_strobe_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.underscan_factor	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.writeback_max_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.writeback_max_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.writeback_min_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.writeback_min_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.xfc_fill_bw_overhead_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.dcn_downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.dfs_vco_period_ps	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.dispclk_dppclk_vco_speed_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.dram_channel_width_bytes	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.dram_clock_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.dram_page_open_time_ns	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.dram_return_buffer_per_channel_bytes	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.dram_rw_turnaround_time_ns	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.dummy_pstate_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.fabric_datapath_to_dcn_data_return_bytes	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.fclk_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.ideal_dram_bw_after_urgent_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.mall_allocated_for_dcn_mbytes	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.max_avg_dram_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.max_avg_dram_bw_use_normal_strobe_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.max_avg_fabric_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.max_avg_sdp_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.max_vratio_pre	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.min_dcfclk	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.pct_ideal_dram_bw_after_urgent_strobe	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.pct_ideal_fabric_bw_after_urgent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.pct_ideal_sdp_bw_after_urgent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.smn_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.sr_enter_plus_exit_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.sr_enter_plus_exit_z8_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.sr_exit_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.sr_exit_z8_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.urgent_latency_adjustment_fabric_clock_component_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.urgent_latency_adjustment_fabric_clock_reference_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.urgent_latency_pixel_data_only_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.urgent_latency_pixel_mixed_with_vm_data_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.urgent_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.urgent_latency_vm_data_only_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.usr_retraining_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.writeback_dram_clock_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.writeback_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.xfc_bus_transport_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.xfc_xbuf_latency_tolerance_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.AverageDCCCompressionRate	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.AverageReadBandwidth	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.AverageReadBandwidthGBytePerSecond	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.BPP	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.BandwidthAvailableForImmediateFlip	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.CriticalPoint	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.CursorBufferSize	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.CursorChunkSize	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DCFCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DCFCLKDeepSleep	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DETBufferSizeInTime	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLKDPPCLKDSCCLKDownSpreading	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLKDPPCLKVCOSpeed	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLKDelaySubtotal	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLKRampingMargin	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLKWithRamping	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLKWithRampingRoundedToDFSGranularity	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLKWithoutRamping	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLKWithoutRampingRoundedToDFSGranularity	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLK_calculated	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DPPCLKDelayCNVCCursor	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DPPCLKDelayCNVCFormater	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DPPCLKDelaySCL	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DPPCLKDelaySCLLBOnly	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DPPCLKDelaySubtotal	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DPPCLKUsingSingleDPPChroma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DPPCLKUsingSingleDPPLuma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DRAMChannelWidth	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DRAMClockChangeLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DRAMClockChangeLatencyOverride	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DRAMClockChangeWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DRAMSpeed	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.Downspreading	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.EffectiveDETLBLinesChroma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.EffectiveDETLBLinesLuma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.EffectiveDETPlusLBLinesChroma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.EffectiveDETPlusLBLinesLuma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.EffectiveFECOverhead	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.ExtraLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.FCLKChangeLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.FECOverhead	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.FabricAndDRAMBandwidth	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.FabricClock	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.FabricDatapathToDCNDataReturn	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.FinalDRAMClockChangeLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.FinalFillLevel	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.FinalFillMargin	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.FractionOfUrgentBandwidth	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.FractionOfUrgentBandwidthImmediateFlip	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.FrameTimeForMinFullDETBufferingTime	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.GPUVMMinPageSize	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.GlobalDPPCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.HostVMMinPageSize	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.InitFillLevel	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.LastPixelOfLineExtraWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.LinesInDETChroma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.LinesInDETLuma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.LinesToFinishSwathTransferStutterCriticalPlane	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaxDCHUBToPSCLThroughput	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaxDispclkRoundedDownToDFSGranularity	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaxDispclkRoundedToDFSGranularity	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaxDppclkRoundedDownToDFSGranularity	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaxHSCLRatio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaxPSCLToLBThroughput	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaxTotalVActiveRDBandwidth	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaxVRatioPre	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaxVSCLRatio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaxVStartup	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaximumReadBandwidthWithPrefetch	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaximumReadBandwidthWithoutPrefetch	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaximumSwathWidthInDETBuffer	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaximumSwathWidthInLineBuffer	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaximumSwathWidthInLineBufferChroma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaximumSwathWidthInLineBufferLuma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaximumSwathWidthSupport	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MinActiveDRAMClockChangeLatencySupported	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MinActiveDRAMClockChangeMargin	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MinActiveFCLKChangeLatencySupported	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MinFullDETBufferingTime	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MinPixelChunkSizeBytes	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MinUrgentLatencySupportUs	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.NextMaxVStartup	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.NonUrgentLatencyTolerance	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.NumberOfChannels	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.Outbpp	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.PDEAndMetaPTEBytesPerFrameC	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.PDEAndMetaPTEBytesPerFrameY	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.PTEGroupSize	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.PartOfBurstThatFitsInROB	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelDataOnly	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencySTROBE	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.PlaneRequiredDISPCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.PlaneRequiredDISPCLKWithODMCombine	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.PlaneRequiredDISPCLKWithODMCombine2To1	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.PlaneRequiredDISPCLKWithODMCombine4To1	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.PlaneRequiredDISPCLKWithoutODMCombine	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.RemainingFillLevel	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.ReturnBW	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.ReturnBWToDCNPerState	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.ReturnBandwidthToDCN	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.ReturnBusWidth	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.RoundTripPingLatencyCycles	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.RoundedUpMaxSwathSizeBytesC	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.RoundedUpMaxSwathSizeBytesY	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.SMNLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.SOCCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.SREnterPlusExitTime	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.SREnterPlusExitZ8Time	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.SRExitTime	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.SRExitZ8Time	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.SmallestVBlank	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.SrcActiveDrainRate	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.StutterBurstTime	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.StutterEfficiency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.StutterEfficiencyNotIncludingVBlank	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.StutterEnterPlusExitWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.StutterExitWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.StutterPeriod	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.StutterPeriodBestCase	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.SurfaceRequiredDISPCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.SurfaceRequiredDISPCLKWithoutODMCombine	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.SwathWidthGranularityC	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.SwathWidthGranularityY	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.SwathWidthYCriticalPlane	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.TCalc	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.TFinalxFill	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.TInitXFill	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.TWait	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.TimeCalc	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.TotalBandwidthConsumedGBytePerSecond	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.TotalDSCUnitsRequired	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.TotalDataReadBandwidth	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.TotalNumberOfActiveOTG	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.TotalRowReadBandwidth	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.TslvChk	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.USRRetrainingLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.UrgentExtraLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.UrgentLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.UrgentLatencyAdjustmentFabricClockComponent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.UrgentLatencyAdjustmentFabricClockReference	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.UrgentLatencyPixelDataOnly	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.UrgentLatencyPixelMixedWithVMData	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.UrgentLatencySupportUsChroma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.UrgentLatencySupportUsLuma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.UrgentLatencyVMDataOnly	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.UrgentOutOfOrderReturnPerChannel	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.UrgentOutOfOrderReturnPerChannelPixelDataOnly	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.UrgentOutOfOrderReturnPerChannelVMDataOnly	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.UrgentRoundTripAndOutOfOrderLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.UrgentWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.VBlankTime	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.VStartupMargin	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.WritebackChromaVExtra	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.WritebackDISPCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.WritebackDRAMClockChangeWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.WritebackInterfaceBufferSize	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.WritebackLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.WritebackLineBufferChromaBufferSize	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.WritebackLineBufferLumaBufferSize	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.WritebackLineBufferSize	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.WritebackLumaVExtra	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.WritebackMaxHSCLRatio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.WritebackMaxHSCLTaps	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.WritebackMaxVSCLRatio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.WritebackMaxVSCLTaps	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.WritebackMinHSCLRatio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.WritebackMinVSCLRatio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.WritebackRequiredDISPCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.WritebackUrgentWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.XFCBusTransportTime	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.XFCFillBWOverhead	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.XFCFillConstant	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.XFCRemoteSurfaceFlipDelay	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.XFCSlvChunkSize	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.XFCTSlvVreadyOffset	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.XFCTSlvVupdateOffset	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.XFCTSlvVupdateWidth	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.XFCXBUFLatencyTolerance	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.Z8StutterEfficiency	-9.223372e+18-9.223372e+18
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PARAM_VALUE	0	state->bw_ctx.dml.vba.Z8StutterEfficiencyNotIncludingVBlank	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.Z8StutterEfficiencyNotIncludingVBlankBestCase	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.Z8StutterEnterPlusExitWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.Z8StutterExitWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.bpp	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.dst_x_after_scaler	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.dst_y_after_scaler	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.dummy5	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.dummy6	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.ip.dcfclk_cstate_latency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.ip.dispclk_ramp_margin_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.ip.dsc_delay_factor_wa	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.ip.max_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.ip.max_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.ip.min_prefetch_in_strobe_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.ip.underscan_factor	-9.223372e+18-9.223372e+18
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PARAM_VALUE	0	state->bw_ctx.dml.vba.ip.writeback_max_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.ip.writeback_min_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.ip.writeback_min_vscl_ratio	-9.223372e+18-9.223372e+18
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PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.dcn_downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.dfs_vco_period_ps	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.dispclk_dppclk_vco_speed_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.downspread_percent	-9.223372e+18-9.223372e+18
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PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.dram_clock_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.dram_page_open_time_ns	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.dram_return_buffer_per_channel_bytes	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.dram_rw_turnaround_time_ns	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.dummy_pstate_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.fabric_datapath_to_dcn_data_return_bytes	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.fclk_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.ideal_dram_bw_after_urgent_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.mall_allocated_for_dcn_mbytes	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.max_avg_dram_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.max_avg_dram_bw_use_normal_strobe_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.max_avg_fabric_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.max_avg_sdp_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.max_vratio_pre	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.min_dcfclk	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.pct_ideal_dram_bw_after_urgent_strobe	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.pct_ideal_fabric_bw_after_urgent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.pct_ideal_sdp_bw_after_urgent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.smn_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.sr_enter_plus_exit_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.sr_enter_plus_exit_z8_time_us	-9.223372e+18-9.223372e+18
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PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.sr_exit_z8_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.urgent_latency_adjustment_fabric_clock_component_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.urgent_latency_adjustment_fabric_clock_reference_mhz	-9.223372e+18-9.223372e+18
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PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.urgent_latency_pixel_mixed_with_vm_data_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.urgent_latency_us	-9.223372e+18-9.223372e+18
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PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.usr_retraining_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.writeback_dram_clock_change_latency_us	-9.223372e+18-9.223372e+18
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PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.xfc_bus_transport_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.xfc_xbuf_latency_tolerance_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.total_dcn_read_bw_with_flip	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.total_dcn_read_bw_with_flip_no_urgent_burst	-9.223372e+18-9.223372e+18
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PARAM_VALUE	0	state->dcn_bw_vars.acceptable_quality_vta_ps	-9223372036854775808.000000-9223372036854775808.000000
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PARAM_VALUE	0	state->dcn_bw_vars.active_dram_clock_change_latency_margin_c	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.active_dram_clock_change_latency_margin_y	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.average_read_bandwidth_gbyte_per_second	-9223372036854775808.000000-9223372036854775808.000000
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PARAM_VALUE	0	state->dcn_bw_vars.block_height256_bytes_c	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.block_height256_bytes_y	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.bw_available_for_immediate_flip	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.byte_per_pix_detc	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.byte_per_pix_dety	-9223372036854775808.000000-9223372036854775808.000000
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PARAM_VALUE	0	state->dcn_bw_vars.pixel_pte_req_height_y	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.pixel_pte_req_width_c	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.pixel_pte_req_width_y	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.prefetch_mode	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.projected_dcfclk_deep_sleep	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.pte_buffer_size_in_requests	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.pte_chunk_size	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.ptemeta_urgent_watermark	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.read256_bytes_block_height_c	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.read256_bytes_block_height_y	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.read256_bytes_block_width_c	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.read256_bytes_block_width_y	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.required_output_bw	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.required_prefetch_pix_data_bw	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.return_bandwidth_to_dcn	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.return_bus_width	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.return_bw	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.return_bw_todcn_per_state	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.rob_buffer_size_in_kbyte	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.round_trip_ping_latency_cycles	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.rounded_up_max_swath_size_bytes_c	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.rounded_up_max_swath_size_bytes_y	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.second_min_active_dram_clock_change_margin	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.smallest_vblank	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.socclk	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.sr_enter_plus_exit_time	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.sr_exit_time	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.stutter_burst_time	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.stutter_efficiency	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.stutter_efficiency_not_including_vblank	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.stutter_enter_plus_exit_watermark	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.stutter_exit_watermark	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.swath_width	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.swath_width_granularity_c	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.swath_width_granularity_y	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.t_calc	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.t_setup	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.t_wait	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.time_calc	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.time_for_fetching_meta_pte	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.time_for_fetching_row_in_vblank	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.time_for_meta_and_dpte_row_with_immediate_flip	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.time_for_meta_and_dpte_row_without_immediate_flip	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.time_for_meta_pte_with_immediate_flip	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.time_for_meta_pte_without_immediate_flip	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.time_setup	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.tot_immediate_flip_bytes	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.total_active_dpp	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.total_active_writeback	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.total_bandwidth_consumed_gbyte_per_second	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.total_data_read_bandwidth	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.total_dcc_active_dpp	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.total_number_of_active_writeback	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.total_read_bandwidth_consumed_gbyte_per_second	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.total_repeater_delay	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.total_repeater_delay_time	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.total_write_bandwidth_consumed_gbyte_per_second	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.under_scan_factor	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.urgent_extra_latency	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.urgent_latency	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.urgent_latency_support_us_chroma	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.urgent_latency_support_us_luma	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.urgent_out_of_order_return_per_channel	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.urgent_round_trip_and_out_of_order_latency	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.urgent_watermark	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.v_blank_of_min_active_dram_clock_change_margin	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.v_blank_time	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.v_init_c	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.v_init_y	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.v_startup_lines	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.vmm_page_size	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.voltage_level_with_immediate_flip	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.voltage_level_without_immediate_flip	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.wr_bandwidth	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.write_back_latency	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.writeback_chroma_buffer_size	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.writeback_chunk_size	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.writeback_dram_clock_change_latency_margin	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.writeback_dram_clock_change_watermark	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.writeback_luma_buffer_size	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->refcount.refcount.refs.counter	1
BUF_SIZE	0	state	381336
BUF_SIZE	0	state	381336
DATA_SOURCE	0	state	r dc_state_create_copy
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
HALF_LOCKED2		&aconnector->hpd_lock
HALF_LOCKED2		&adev->dm.dc_lock
HALF_LOCKED2		&attr->mutex
HALF_LOCKED2		&dm->dc_lock
HALF_LOCKED2		_T->lock

drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c dc_commit_streams() -> dc_state_release()

Type	Parameter	Key	Value
PARAM_VALUE	0	state	4096-ptr_max
PARAM_VALUE	0	state->bw_ctx.dml.ip.dcfclk_cstate_latency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.dispclk_ramp_margin_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.dsc_delay_factor_wa	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.max_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.max_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.min_prefetch_in_strobe_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.underscan_factor	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.writeback_max_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.writeback_max_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.writeback_min_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.writeback_min_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.xfc_fill_bw_overhead_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.dcn_downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.dfs_vco_period_ps	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.dispclk_dppclk_vco_speed_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.dram_channel_width_bytes	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.dram_clock_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.dram_page_open_time_ns	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.dram_return_buffer_per_channel_bytes	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.dram_rw_turnaround_time_ns	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.dummy_pstate_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.fabric_datapath_to_dcn_data_return_bytes	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.fclk_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.ideal_dram_bw_after_urgent_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.mall_allocated_for_dcn_mbytes	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.max_avg_dram_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.max_avg_dram_bw_use_normal_strobe_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.max_avg_fabric_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.max_avg_sdp_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.max_vratio_pre	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.min_dcfclk	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.pct_ideal_dram_bw_after_urgent_strobe	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.pct_ideal_fabric_bw_after_urgent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.pct_ideal_sdp_bw_after_urgent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.smn_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.sr_enter_plus_exit_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.sr_enter_plus_exit_z8_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.sr_exit_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.sr_exit_z8_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.urgent_latency_adjustment_fabric_clock_component_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.urgent_latency_adjustment_fabric_clock_reference_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.urgent_latency_pixel_data_only_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.urgent_latency_pixel_mixed_with_vm_data_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.urgent_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.urgent_latency_vm_data_only_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.usr_retraining_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.writeback_dram_clock_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.writeback_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.xfc_bus_transport_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.xfc_xbuf_latency_tolerance_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.AverageDCCCompressionRate	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.AverageReadBandwidth	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.AverageReadBandwidthGBytePerSecond	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.BPP	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.BandwidthAvailableForImmediateFlip	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.CriticalPoint	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.CursorBufferSize	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.CursorChunkSize	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DCFCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DCFCLKDeepSleep	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DETBufferSizeInTime	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLKDPPCLKDSCCLKDownSpreading	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLKDPPCLKVCOSpeed	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLKDelaySubtotal	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLKRampingMargin	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLKWithRamping	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLKWithRampingRoundedToDFSGranularity	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLKWithoutRamping	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLKWithoutRampingRoundedToDFSGranularity	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLK_calculated	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DPPCLKDelayCNVCCursor	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DPPCLKDelayCNVCFormater	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DPPCLKDelaySCL	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DPPCLKDelaySCLLBOnly	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DPPCLKDelaySubtotal	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DPPCLKUsingSingleDPPChroma	-1.797693e+308-1.797693e+308
PARAM_VALUE	0	state->bw_ctx.dml.vba.DPPCLKUsingSingleDPPLuma	-1.797693e+308-1.797693e+308
PARAM_VALUE	0	state->bw_ctx.dml.vba.DRAMChannelWidth	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DRAMClockChangeLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DRAMClockChangeLatencyOverride	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DRAMClockChangeWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DRAMSpeed	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.Downspreading	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.EffectiveDETLBLinesChroma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.EffectiveDETLBLinesLuma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.EffectiveDETPlusLBLinesChroma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.EffectiveDETPlusLBLinesLuma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.EffectiveFECOverhead	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.ExtraLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.FCLKChangeLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.FECOverhead	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.FabricAndDRAMBandwidth	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.FabricClock	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.FabricDatapathToDCNDataReturn	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.FinalDRAMClockChangeLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.FinalFillLevel	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.FinalFillMargin	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.FractionOfUrgentBandwidth	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.FractionOfUrgentBandwidthImmediateFlip	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.FrameTimeForMinFullDETBufferingTime	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.GPUVMMinPageSize	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.GlobalDPPCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.HostVMMinPageSize	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.InitFillLevel	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.LastPixelOfLineExtraWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.LinesInDETChroma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.LinesInDETLuma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.LinesToFinishSwathTransferStutterCriticalPlane	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaxDCHUBToPSCLThroughput	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaxDispclkRoundedDownToDFSGranularity	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaxDispclkRoundedToDFSGranularity	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaxDppclkRoundedDownToDFSGranularity	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaxHSCLRatio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaxPSCLToLBThroughput	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaxTotalVActiveRDBandwidth	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaxVRatioPre	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaxVSCLRatio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaxVStartup	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaximumReadBandwidthWithPrefetch	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaximumReadBandwidthWithoutPrefetch	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaximumSwathWidthInDETBuffer	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaximumSwathWidthInLineBuffer	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaximumSwathWidthInLineBufferChroma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaximumSwathWidthInLineBufferLuma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaximumSwathWidthSupport	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MinActiveDRAMClockChangeLatencySupported	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MinActiveDRAMClockChangeMargin	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MinActiveFCLKChangeLatencySupported	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MinFullDETBufferingTime	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MinPixelChunkSizeBytes	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MinUrgentLatencySupportUs	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.NextMaxVStartup	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.NonUrgentLatencyTolerance	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.NumberOfChannels	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.Outbpp	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.PDEAndMetaPTEBytesPerFrameC	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.PDEAndMetaPTEBytesPerFrameY	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.PTEGroupSize	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.PartOfBurstThatFitsInROB	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelDataOnly	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencySTROBE	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.PlaneRequiredDISPCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.PlaneRequiredDISPCLKWithODMCombine	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.PlaneRequiredDISPCLKWithODMCombine2To1	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.PlaneRequiredDISPCLKWithODMCombine4To1	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.PlaneRequiredDISPCLKWithoutODMCombine	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.RemainingFillLevel	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.ReturnBW	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.ReturnBWToDCNPerState	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.ReturnBandwidthToDCN	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.ReturnBusWidth	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.RoundTripPingLatencyCycles	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.RoundedUpMaxSwathSizeBytesC	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.RoundedUpMaxSwathSizeBytesY	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.SMNLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.SOCCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.SREnterPlusExitTime	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.SREnterPlusExitZ8Time	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.SRExitTime	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.SRExitZ8Time	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.SmallestVBlank	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.SrcActiveDrainRate	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.StutterBurstTime	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.StutterEfficiency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.StutterEfficiencyNotIncludingVBlank	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.StutterEnterPlusExitWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.StutterExitWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.StutterPeriod	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.StutterPeriodBestCase	-9.223372e+18-9.223372e+18
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PARAM_VALUE	0	state->bw_ctx.dml.vba.SurfaceRequiredDISPCLKWithoutODMCombine	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.SwathWidthGranularityC	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.SwathWidthGranularityY	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.SwathWidthYCriticalPlane	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.TCalc	-9.223372e+18-9.223372e+18
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PARAM_VALUE	0	state->bw_ctx.dml.vba.TInitXFill	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.TWait	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.TimeCalc	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.TotalBandwidthConsumedGBytePerSecond	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.TotalDSCUnitsRequired	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.TotalDataReadBandwidth	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.TotalNumberOfActiveOTG	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.TotalRowReadBandwidth	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.TslvChk	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.USRRetrainingLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.UrgentExtraLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.UrgentLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.UrgentLatencyAdjustmentFabricClockComponent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.UrgentLatencyAdjustmentFabricClockReference	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.UrgentLatencyPixelDataOnly	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.UrgentLatencyPixelMixedWithVMData	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.UrgentLatencySupportUsChroma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.UrgentLatencySupportUsLuma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.UrgentLatencyVMDataOnly	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.UrgentOutOfOrderReturnPerChannel	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.UrgentOutOfOrderReturnPerChannelPixelDataOnly	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.UrgentOutOfOrderReturnPerChannelVMDataOnly	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.UrgentRoundTripAndOutOfOrderLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.UrgentWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.VBlankTime	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.VStartupMargin	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.Watermark.DRAMClockChangeWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.Watermark.FCLKChangeWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.Watermark.StutterEnterPlusExitWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.Watermark.StutterExitWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.Watermark.USRRetrainingWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.Watermark.UrgentWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.Watermark.WritebackDRAMClockChangeWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.Watermark.WritebackFCLKChangeWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.Watermark.WritebackUrgentWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.Watermark.Z8StutterEnterPlusExitWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.Watermark.Z8StutterExitWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.WritebackChromaVExtra	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.WritebackDISPCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.WritebackDRAMClockChangeWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.WritebackInterfaceBufferSize	-9.223372e+18-9.223372e+18
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PARAM_VALUE	0	state->bw_ctx.dml.vba.WritebackLineBufferChromaBufferSize	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.WritebackLineBufferLumaBufferSize	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.WritebackLineBufferSize	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.WritebackLumaVExtra	-9.223372e+18-9.223372e+18
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PARAM_VALUE	0	state->bw_ctx.dml.vba.WritebackMaxHSCLTaps	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.WritebackMaxVSCLRatio	-9.223372e+18-9.223372e+18
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PARAM_VALUE	0	state->bw_ctx.dml.vba.WritebackUrgentWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.XFCBusTransportTime	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.XFCFillBWOverhead	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.XFCFillConstant	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.XFCRemoteSurfaceFlipDelay	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.XFCSlvChunkSize	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.XFCTSlvVreadyOffset	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.XFCTSlvVupdateOffset	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.XFCTSlvVupdateWidth	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.XFCXBUFLatencyTolerance	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.Z8StutterEfficiency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.Z8StutterEfficiencyBestCase	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.Z8StutterEfficiencyNotIncludingVBlank	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.Z8StutterEfficiencyNotIncludingVBlankBestCase	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.Z8StutterEnterPlusExitWatermark	-9.223372e+18-9.223372e+18
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PARAM_VALUE	0	state->bw_ctx.dml.vba.bpp	-9.223372e+18-9.223372e+18
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PARAM_VALUE	0	state->res_ctx.temp_pipe.dml_dlg_sys_param.t_extra_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->res_ctx.temp_pipe.dml_dlg_sys_param.t_mclk_wm_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->res_ctx.temp_pipe.dml_dlg_sys_param.t_sr_wm_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->res_ctx.temp_pipe.dml_dlg_sys_param.t_urg_wm_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->res_ctx.temp_pipe.dml_dlg_sys_param.total_flip_bw	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->res_ctx.temp_pipe.dml_input.clks_cfg.dcfclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->res_ctx.temp_pipe.dml_input.clks_cfg.dispclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->res_ctx.temp_pipe.dml_input.clks_cfg.dppclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->res_ctx.temp_pipe.dml_input.clks_cfg.refclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->res_ctx.temp_pipe.dml_input.clks_cfg.socclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->res_ctx.temp_pipe.dml_input.dout.output_bpp	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->res_ctx.temp_pipe.dml_input.dout.wb.wb_hratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->res_ctx.temp_pipe.dml_input.dout.wb.wb_vratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->res_ctx.temp_pipe.dml_input.pipe.dest.pixel_rate_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->res_ctx.temp_pipe.dml_input.pipe.scale_ratio_depth.hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->res_ctx.temp_pipe.dml_input.pipe.scale_ratio_depth.hscl_ratio_c	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->res_ctx.temp_pipe.dml_input.pipe.scale_ratio_depth.vinit	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->res_ctx.temp_pipe.dml_input.pipe.scale_ratio_depth.vinit_bot	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->res_ctx.temp_pipe.dml_input.pipe.scale_ratio_depth.vinit_bot_c	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->res_ctx.temp_pipe.dml_input.pipe.scale_ratio_depth.vinit_c	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->res_ctx.temp_pipe.dml_input.pipe.scale_ratio_depth.vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->res_ctx.temp_pipe.dml_input.pipe.scale_ratio_depth.vscl_ratio_c	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->res_ctx.temp_pipe.dml_input.pipe.src.dcc_fraction_of_zs_req_chroma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->res_ctx.temp_pipe.dml_input.pipe.src.dcc_fraction_of_zs_req_luma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->res_ctx.temp_pipe.dml_input.pipe.src.xfc_params.xfc_tslv_vready_offset_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->res_ctx.temp_pipe.dml_input.pipe.src.xfc_params.xfc_tslv_vupdate_offset_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->res_ctx.temp_pipe.dml_input.pipe.src.xfc_params.xfc_tslv_vupdate_width_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->res_ctx.temp_pipe.pipe_dlg_param.pixel_rate_mhz	-9.223372e+18-9.223372e+18
BUF_SIZE	0	state	381336
BUF_SIZE	0	state	381336
CAPPED_DATA	0	state	1
DATA_SOURCE	0	state	r dc_state_create_current_copy
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
LOCK2		&dm->dc_lock
HALF_LOCKED2		&adev->reset_domain->sem
HALF_LOCKED2		&of->mutex
HALF_LOCKED2		&pool->lock
HALF_LOCKED2		global &drm_unplug_srcu
TYPE_LOCK		(struct amdgpu_display_manager)->dc_lock

drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c dc_destruct() -> dc_state_release()

Type	Parameter	Key	Value
PARAM_VALUE	0	state	1-u64max
PARAM_VALUE	0	*state->res_ctx.link_enc_cfg_ctx.link_enc_avail	s32min-s32max
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
HALF_LOCKED2		_T->lock

drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c release_minimal_transition_state() -> dc_state_release()

Type	Parameter	Key	Value
PARAM_VALUE	0	state->bw_ctx.dml.vba.DPPCLKUsingSingleDPPChroma	-1.797693e+308-1.797693e+308
PARAM_VALUE	0	state->bw_ctx.dml.vba.DPPCLKUsingSingleDPPLuma	-1.797693e+308-1.797693e+308
BUF_SIZE	0	state	(-1),370336,381336
BUF_SIZE	0	state	(-1),370336,381336
DATA_SOURCE	0	state	$1
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL

drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c swap_and_release_current_context() -> dc_state_release()

Type	Parameter	Key	Value
NOCHECK_CALL

drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c update_planes_and_stream_cleanup_v3() -> dc_state_release()

Type	Parameter	Key	Value
NOCHECK_CALL

drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c update_planes_and_stream_cleanup_v3() -> dc_state_release()

Type	Parameter	Key	Value
NOCHECK_CALL

drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c __free_state_release() -> dc_state_release()

Type	Parameter	Key	Value
PARAM_VALUE	0	state	1-u64max
BIT_INFO	0	state	0x0,0x7fffffffffffffff
BIT_INFO	0	state	0x0,0x7fffffffffffffff
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
LOCK2		&dm->dc_lock
HALF_LOCKED2		&adev->reset_domain->sem
HALF_LOCKED2		&of->mutex
HALF_LOCKED2		&pool->lock
HALF_LOCKED2		global &drm_unplug_srcu
TYPE_LOCK		(struct amdgpu_display_manager)->dc_lock

drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c dm_atomic_destroy_state() -> dc_state_release()

Type	Parameter	Key	Value
PARAM_VALUE	0	state	1-u64max
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL

drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c dm_resume() -> dc_state_release()

Type	Parameter	Key	Value
PARAM_VALUE	0	state	4096-ptr_max
CAPPED_DATA	0	state->stream_count	1
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
HALF_LOCKED2		&adev->reset_domain->sem
HALF_LOCKED2		&dm->dc_lock
HALF_LOCKED2		&of->mutex
HALF_LOCKED2		&pool->lock
HALF_LOCKED2		global &drm_unplug_srcu

drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c dm_resume() -> dc_state_release()

Type	Parameter	Key	Value
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
HALF_LOCKED2		&adev->reset_domain->sem
HALF_LOCKED2		&dm->dc_lock
HALF_LOCKED2		&of->mutex
HALF_LOCKED2		&pool->lock
HALF_LOCKED2		global &drm_unplug_srcu

drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_state.c dc_state_create() -> dc_state_release()

Type	Parameter	Key	Value
PARAM_VALUE	0	state	4096-ptr_max
PARAM_VALUE	0	state->bw_ctx.dml.soc.dispclk_dppclk_vco_speed_mhz	-1.797693e+308-1.797693e+308
PARAM_VALUE	0	state->bw_ctx.dml2	0,4096-ptr_max
PARAM_VALUE	0	state->bw_ctx.dml2->config.bbox_overrides.dchub_refclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->config.bbox_overrides.disp_pll_vco_speed_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->config.bbox_overrides.dprefclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->config.bbox_overrides.dram_clock_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->config.bbox_overrides.fclk_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->config.bbox_overrides.sr_enter_plus_exit_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->config.bbox_overrides.sr_enter_plus_exit_z8_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->config.bbox_overrides.sr_exit_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->config.bbox_overrides.sr_exit_z8_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->config.bbox_overrides.urgent_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->config.bbox_overrides.xtalclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ip.dispclk_ramp_margin_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ip.max_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ip.max_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ip.writeback_max_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ip.writeback_max_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ip.writeback_min_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ip.writeback_min_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.BandwidthAvailableForImmediateFlip	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.DCFCLKDeepSleep	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Dcfclk	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Dispclk	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Dispclk_calculated	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.FractionOfUrgentBandwidth	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.FractionOfUrgentBandwidthImmediateFlip	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.GlobalDPPCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.MaxActiveFCLKChangeLatencySupported	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.StutterEfficiency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.StutterEfficiencyNotIncludingVBlank	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.StutterPeriod	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.StutterPeriodBestCase	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.TCalc	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.TotalDataReadBandwidth	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.UrgentExtraLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.UrgentLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.UrgentLatencyWithUSRRetraining	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Watermark.DRAMClockChangeWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Watermark.FCLKChangeWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Watermark.StutterEnterPlusExitWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Watermark.StutterExitWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Watermark.USRRetrainingWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Watermark.UrgentWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Watermark.WritebackDRAMClockChangeWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Watermark.WritebackFCLKChangeWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Watermark.WritebackUrgentWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Watermark.Z8StutterEnterPlusExitWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Watermark.Z8StutterExitWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.WritebackDISPCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Z8StutterEfficiency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Z8StutterEfficiencyBestCase	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Z8StutterEfficiencyNotIncludingVBlank	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.non_urgent_total_dcn_read_bw_with_flip	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.total_dcn_read_bw_with_flip	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.total_dcn_read_bw_with_flip_no_urgent_burst	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.BandwidthAvailableForImmediateFlip	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.DCFCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.DRAMSpeed	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.ExtraLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.FabricClock	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.GlobalDPPCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.MaximumSwathWidthInLineBufferChroma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.MaximumSwathWidthInLineBufferLuma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.ReturnBW	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.ReturnDRAMBW	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.SOCCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.TWait	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.TimeCalc	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.UrgLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.WritebackRequiredDISPCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.ip.dispclk_ramp_margin_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.ip.max_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.ip.max_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.ip.writeback_max_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.ip.writeback_max_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.ip.writeback_min_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.ip.writeback_min_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.dcfclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.dispclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.dppclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.dram_clock_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.dram_speed_mts	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.dscclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.dtbclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.fabricclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.fclk_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.g6_temp_read_blackout_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.phyclk_d18_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.phyclk_d32_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.phyclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.socclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.sr_enter_plus_exit_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.sr_enter_plus_exit_z8_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.sr_exit_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.sr_exit_z8_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.urgent_latency_pixel_data_only_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.urgent_latency_vm_data_only_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.usr_retraining_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.writeback_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.amclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.dcn_downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.dispclk_dppclk_vco_speed_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.dprefclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.max_avg_dram_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.max_avg_fabric_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.max_avg_sdp_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.pcierefclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.pct_ideal_dram_bw_after_urgent_strobe	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.pct_ideal_dram_bw_after_urgent_vm_only	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.pct_ideal_fabric_bw_after_urgent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.pct_ideal_sdp_bw_after_urgent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.phy_downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.refclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.smn_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.xtalclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.dcfclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.dispclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.dppclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.dram_clock_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.dram_speed_mts	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.dscclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.dtbclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.fabricclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.fclk_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.g6_temp_read_blackout_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.phyclk_d18_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.phyclk_d32_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.phyclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.socclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.sr_enter_plus_exit_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.sr_enter_plus_exit_z8_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.sr_exit_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.sr_exit_z8_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.urgent_latency_pixel_data_only_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.urgent_latency_vm_data_only_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.usr_retraining_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.writeback_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.amclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.dcn_downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.dispclk_dppclk_vco_speed_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.dprefclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.max_avg_dram_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.max_avg_dram_bw_use_normal_strobe_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.max_avg_fabric_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.max_avg_sdp_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.pcierefclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.pct_ideal_dram_bw_after_urgent_pixel_only	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.pct_ideal_dram_bw_after_urgent_strobe	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.pct_ideal_dram_bw_after_urgent_vm_only	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.pct_ideal_fabric_bw_after_urgent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.pct_ideal_sdp_bw_after_urgent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.phy_downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.refclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.smn_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.svp_prefetch_pct_ideal_sdp_bw_after_urgent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.xtalclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.display_config.overrides.hw.dcfclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.display_config.overrides.hw.dispclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.display_config.overrides.hw.dlg_ref_clk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.dml_init.soc_bb.dcn_downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.dml_init.soc_bb.dispclk_dppclk_vco_speed_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.dml_init.soc_bb.fraction_of_urgent_bandwidth_flip_target	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.dml_init.soc_bb.fraction_of_urgent_bandwidth_nominal_target	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.dml_init.soc_bb.lower_bound_bandwidth_dchub	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.dml_init.soc_bb.phy_downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.mode_programming.dml2_instance->funcs.check_mode_supported	0,6573368814298443776
PARAM_VALUE	0	state->bw_ctx.dml2->v21.mode_programming.dml2_instance->project_id	0-4
PARAM_VALUE	0	state->bw_ctx.dml2->v21.mode_support.dml2_instance->funcs.build_mcache_programming	0,5655262704298098688
PARAM_VALUE	0	state->bw_ctx.dml2->v21.mode_support.dml2_instance->funcs.build_mode_programming	0,7150732188596219904
PARAM_VALUE	0	state->bw_ctx.dml2->v21.mode_support.dml2_instance->funcs.check_mode_supported	0,6573368814298443776
PARAM_VALUE	0	state->bw_ctx.dml2->v21.mode_support.dml2_instance->project_id	0-4
PARAM_VALUE	0	state->power_source	0
PARAM_VALUE	0	state->res_ctx.link_enc_cfg_ctx.mode	0
PARAM_VALUE	0	*state->res_ctx.link_enc_cfg_ctx.link_enc_avail	(-1)-4
BUF_SIZE	0	state	385448
DATA_SOURCE	0	state	r __kvmalloc_node_noprof
PREEMPT_ADD			<- disables preempt
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL

drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_state.c dc_state_create() -> dc_state_release()

Type	Parameter	Key	Value
PARAM_VALUE	0	state	4096-ptr_max
PARAM_VALUE	0	state->bw_ctx.dml.soc.dispclk_dppclk_vco_speed_mhz	-1.797693e+308-1.797693e+308
PARAM_VALUE	0	state->bw_ctx.dml2	1-u64max
PARAM_VALUE	0	state->bw_ctx.dml2->architecture	0-4294967295
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ip.config_return_buffer_segment_size_in_kbytes	0-4294967295
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.project	0-4294967295
PARAM_VALUE	0	state->bw_ctx.dml2->v20.scratch.build_synthetic_socbb_params.in_states->num_states	0-4294967295
PARAM_VALUE	0	state->bw_ctx.dml2->v20.scratch.build_synthetic_socbb_params.num_dcfclk_stas	s32min-s32max
PARAM_VALUE	0	state->bw_ctx.dml2->v21.mode_programming.dml2_instance->project_id	0-4294967295
PARAM_VALUE	0	state->bw_ctx.dml2->v21.mode_support.dml2_instance->project_id	0-4294967295
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source	0,4096-ptr_max
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->config.bbox_overrides.dchub_refclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->config.bbox_overrides.disp_pll_vco_speed_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->config.bbox_overrides.dprefclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->config.bbox_overrides.fclk_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->config.bbox_overrides.sr_exit_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->config.bbox_overrides.sr_exit_z8_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->config.bbox_overrides.urgent_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->config.bbox_overrides.xtalclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ip.dispclk_ramp_margin_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ip.max_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ip.max_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ip.writeback_max_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ip.writeback_max_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ip.writeback_min_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ip.writeback_min_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.mp.DCFCLKDeepSleep	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.mp.Dcfclk	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.mp.Dispclk	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.mp.Dispclk_calculated	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.mp.FractionOfUrgentBandwidth	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.mp.GlobalDPPCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.mp.StutterEfficiency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.mp.StutterPeriod	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.mp.StutterPeriodBestCase	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.mp.TCalc	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.mp.TotalDataReadBandwidth	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.mp.UrgentExtraLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.mp.UrgentLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.mp.Watermark.UrgentWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.mp.WritebackDISPCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.mp.Z8StutterEfficiency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.mp.Z8StutterEfficiencyBestCase	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.mp.total_dcn_read_bw_with_flip	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.DCFCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.DRAMSpeed	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.ExtraLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.FabricClock	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.GlobalDPPCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.ReturnBW	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.ReturnDRAMBW	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.SOCCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.TWait	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.TimeCalc	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.UrgLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.WritebackRequiredDISPCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.ip.max_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.ip.max_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.ip.writeback_max_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.ip.writeback_max_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.ip.writeback_min_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.ip.writeback_min_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.max_state.dcfclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.max_state.dispclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.max_state.dppclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.max_state.dram_speed_mts	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.max_state.dscclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.max_state.dtbclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.max_state.fabricclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.max_state.phyclk_d18_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.max_state.phyclk_d32_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.max_state.phyclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.max_state.socclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.max_state.sr_exit_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.soc.amclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.soc.dcn_downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.soc.dprefclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.soc.pcierefclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.soc.phy_downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.soc.refclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.soc.smn_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.soc.xtalclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.state.dcfclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.state.dispclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.state.dppclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.state.dram_speed_mts	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.state.dscclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.state.dtbclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.state.fabricclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.state.phyclk_d18_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.state.phyclk_d32_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.state.phyclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.state.socclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.state.sr_exit_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.state.sr_exit_z8_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.state.writeback_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.soc.amclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.soc.dcn_downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.soc.dprefclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.soc.pcierefclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.soc.phy_downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.soc.refclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.soc.smn_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.soc.xtalclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v21.display_config.overrides.hw.dcfclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v21.display_config.overrides.hw.dispclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v21.display_config.overrides.hw.dlg_ref_clk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v21.dml_init.soc_bb.dcn_downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v21.dml_init.soc_bb.lower_bound_bandwidth_dchub	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v21.dml_init.soc_bb.phy_downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v21.mode_programming.dml2_instance->project_id	0-4
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v21.mode_support.dml2_instance->project_id	0-4
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v21.scratch.temp_pipe.dml_input.dout.output_bpp	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->power_source	0
PARAM_VALUE	0	state->res_ctx.link_enc_cfg_ctx.mode	0
PARAM_VALUE	0	*state->res_ctx.link_enc_cfg_ctx.link_enc_avail	(-1)-4
BUF_SIZE	0	state	385448
DATA_SOURCE	0	state	r __kvmalloc_node_noprof
PREEMPT_ADD			<- disables preempt
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL

drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_state.c dc_state_create_copy() -> dc_state_release()

Type	Parameter	Key	Value
PARAM_VALUE	0	state	4096-ptr_max
PARAM_VALUE	0	state->bw_ctx.dml.ip.dcfclk_cstate_latency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.dispclk_ramp_margin_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.dsc_delay_factor_wa	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.max_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.max_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.min_prefetch_in_strobe_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.underscan_factor	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.writeback_max_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.writeback_max_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.writeback_min_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.writeback_min_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.xfc_fill_bw_overhead_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.dcn_downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.dfs_vco_period_ps	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.dispclk_dppclk_vco_speed_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.dram_channel_width_bytes	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.dram_clock_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.dram_page_open_time_ns	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.dram_return_buffer_per_channel_bytes	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.dram_rw_turnaround_time_ns	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.dummy_pstate_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.fabric_datapath_to_dcn_data_return_bytes	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.fclk_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.ideal_dram_bw_after_urgent_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.mall_allocated_for_dcn_mbytes	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.max_avg_dram_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.max_avg_dram_bw_use_normal_strobe_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.max_avg_fabric_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.max_avg_sdp_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.max_vratio_pre	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.min_dcfclk	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.pct_ideal_dram_bw_after_urgent_strobe	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.pct_ideal_fabric_bw_after_urgent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.pct_ideal_sdp_bw_after_urgent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.smn_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.sr_enter_plus_exit_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.sr_enter_plus_exit_z8_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.sr_exit_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.sr_exit_z8_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.urgent_latency_adjustment_fabric_clock_component_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.urgent_latency_adjustment_fabric_clock_reference_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.urgent_latency_pixel_data_only_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.urgent_latency_pixel_mixed_with_vm_data_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.urgent_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.urgent_latency_vm_data_only_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.usr_retraining_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.writeback_dram_clock_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.writeback_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.xfc_bus_transport_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.xfc_xbuf_latency_tolerance_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.AverageDCCCompressionRate	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.AverageReadBandwidth	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.AverageReadBandwidthGBytePerSecond	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.BPP	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.BandwidthAvailableForImmediateFlip	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.CriticalPoint	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.CursorBufferSize	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.CursorChunkSize	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DCFCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DCFCLKDeepSleep	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DETBufferSizeInTime	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLKDPPCLKDSCCLKDownSpreading	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLKDPPCLKVCOSpeed	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLKDelaySubtotal	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLKRampingMargin	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLKWithRamping	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLKWithRampingRoundedToDFSGranularity	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLKWithoutRamping	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLKWithoutRampingRoundedToDFSGranularity	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLK_calculated	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DPPCLKDelayCNVCCursor	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DPPCLKDelayCNVCFormater	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DPPCLKDelaySCL	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DPPCLKDelaySCLLBOnly	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DPPCLKDelaySubtotal	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DPPCLKUsingSingleDPPChroma	-1.797693e+308-1.797693e+308
PARAM_VALUE	0	state->bw_ctx.dml.vba.DPPCLKUsingSingleDPPLuma	-1.797693e+308-1.797693e+308
PARAM_VALUE	0	state->bw_ctx.dml.vba.DRAMChannelWidth	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DRAMClockChangeLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DRAMClockChangeLatencyOverride	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DRAMClockChangeWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DRAMSpeed	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.Downspreading	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.EffectiveDETLBLinesChroma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.EffectiveDETLBLinesLuma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.EffectiveDETPlusLBLinesChroma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.EffectiveDETPlusLBLinesLuma	-9.223372e+18-9.223372e+18
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PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.dispclk_dppclk_vco_speed_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.dram_channel_width_bytes	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.dram_clock_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.dram_page_open_time_ns	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.dram_return_buffer_per_channel_bytes	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.dram_rw_turnaround_time_ns	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.dummy_pstate_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.fabric_datapath_to_dcn_data_return_bytes	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.fclk_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.ideal_dram_bw_after_urgent_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.mall_allocated_for_dcn_mbytes	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.max_avg_dram_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.max_avg_dram_bw_use_normal_strobe_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.max_avg_fabric_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.max_avg_sdp_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.max_vratio_pre	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.min_dcfclk	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.pct_ideal_dram_bw_after_urgent_strobe	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.pct_ideal_fabric_bw_after_urgent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.pct_ideal_sdp_bw_after_urgent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.smn_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.sr_enter_plus_exit_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.sr_enter_plus_exit_z8_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.sr_exit_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.sr_exit_z8_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.urgent_latency_adjustment_fabric_clock_component_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.urgent_latency_adjustment_fabric_clock_reference_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.urgent_latency_pixel_data_only_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.urgent_latency_pixel_mixed_with_vm_data_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.urgent_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.urgent_latency_vm_data_only_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.usr_retraining_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.writeback_dram_clock_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.writeback_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.xfc_bus_transport_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.xfc_xbuf_latency_tolerance_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.total_dcn_read_bw_with_flip	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.total_dcn_read_bw_with_flip_no_urgent_burst	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2	0,4096-ptr_max
PARAM_VALUE	0	state->bw_ctx.dml2->config.bbox_overrides.dchub_refclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->config.bbox_overrides.disp_pll_vco_speed_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->config.bbox_overrides.dprefclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->config.bbox_overrides.dram_clock_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->config.bbox_overrides.fclk_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->config.bbox_overrides.sr_enter_plus_exit_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->config.bbox_overrides.sr_enter_plus_exit_z8_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->config.bbox_overrides.sr_exit_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->config.bbox_overrides.sr_exit_z8_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->config.bbox_overrides.urgent_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->config.bbox_overrides.xtalclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ip.dispclk_ramp_margin_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ip.max_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ip.max_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ip.writeback_max_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ip.writeback_max_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ip.writeback_min_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ip.writeback_min_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.BandwidthAvailableForImmediateFlip	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.DCFCLKDeepSleep	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Dcfclk	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Dispclk	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Dispclk_calculated	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.FractionOfUrgentBandwidth	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.FractionOfUrgentBandwidthImmediateFlip	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.GlobalDPPCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.MaxActiveFCLKChangeLatencySupported	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.StutterEfficiency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.StutterEfficiencyNotIncludingVBlank	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.StutterPeriod	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.StutterPeriodBestCase	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.TCalc	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.TotalDataReadBandwidth	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.UrgentExtraLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.UrgentLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.UrgentLatencyWithUSRRetraining	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Watermark.DRAMClockChangeWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Watermark.FCLKChangeWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Watermark.StutterEnterPlusExitWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Watermark.StutterExitWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Watermark.USRRetrainingWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Watermark.UrgentWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Watermark.WritebackDRAMClockChangeWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Watermark.WritebackFCLKChangeWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Watermark.WritebackUrgentWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Watermark.Z8StutterEnterPlusExitWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Watermark.Z8StutterExitWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.WritebackDISPCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Z8StutterEfficiency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Z8StutterEfficiencyBestCase	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Z8StutterEfficiencyNotIncludingVBlank	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.non_urgent_total_dcn_read_bw_with_flip	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.total_dcn_read_bw_with_flip	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.total_dcn_read_bw_with_flip_no_urgent_burst	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.BandwidthAvailableForImmediateFlip	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.DCFCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.DRAMSpeed	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.ExtraLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.FabricClock	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.GlobalDPPCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.MaximumSwathWidthInLineBufferChroma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.MaximumSwathWidthInLineBufferLuma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.ReturnBW	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.ReturnDRAMBW	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.SOCCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.TWait	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.TimeCalc	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.UrgLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.WritebackRequiredDISPCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.cache_display_cfg.clk_overrides.dcfclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.cache_display_cfg.clk_overrides.dispclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.cache_display_cfg.hw.DLGRefClkFreqMHz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.ip.dispclk_ramp_margin_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.ip.max_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.ip.max_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.ip.writeback_max_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.ip.writeback_max_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.ip.writeback_min_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.ip.writeback_min_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.dcfclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.dispclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.dppclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.dram_clock_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.dram_speed_mts	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.dscclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.dtbclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.fabricclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.fclk_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.g6_temp_read_blackout_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.phyclk_d18_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.phyclk_d32_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.phyclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.socclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.sr_enter_plus_exit_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.sr_enter_plus_exit_z8_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.sr_exit_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.sr_exit_z8_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.urgent_latency_pixel_data_only_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.urgent_latency_vm_data_only_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.usr_retraining_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.writeback_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.amclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.dcn_downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.dispclk_dppclk_vco_speed_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.dprefclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.max_avg_dram_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.max_avg_fabric_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.max_avg_sdp_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.pcierefclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.pct_ideal_dram_bw_after_urgent_strobe	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.pct_ideal_dram_bw_after_urgent_vm_only	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.pct_ideal_fabric_bw_after_urgent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.pct_ideal_sdp_bw_after_urgent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.phy_downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.refclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.smn_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.xtalclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.dcfclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.dispclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.dppclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.dram_clock_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.dram_speed_mts	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.dscclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.dtbclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.fabricclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.fclk_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.g6_temp_read_blackout_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.phyclk_d18_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.phyclk_d32_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.phyclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.socclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.sr_enter_plus_exit_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.sr_enter_plus_exit_z8_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.sr_exit_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.sr_exit_z8_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.urgent_latency_pixel_data_only_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.urgent_latency_vm_data_only_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.usr_retraining_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.writeback_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Tdmbf	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Tdmec	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_params.TCalc	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_params.TWait	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.scratch.UseMinimumDCFCLK_locals.DPTEBandwidth	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.scratch.UseMinimumDCFCLK_locals.MinimumTWait	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.scratch.UseMinimumDCFCLK_params.DCFCLKPerState	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.scratch.UseMinimumDCFCLK_params.UrgLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.amclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.dcn_downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.dispclk_dppclk_vco_speed_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.dprefclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.max_avg_dram_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.max_avg_dram_bw_use_normal_strobe_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.max_avg_fabric_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.max_avg_sdp_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.pcierefclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.pct_ideal_dram_bw_after_urgent_pixel_only	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.pct_ideal_dram_bw_after_urgent_strobe	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.pct_ideal_dram_bw_after_urgent_vm_only	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.pct_ideal_fabric_bw_after_urgent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.pct_ideal_sdp_bw_after_urgent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.phy_downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.refclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.smn_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.svp_prefetch_pct_ideal_sdp_bw_after_urgent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.xtalclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.scratch.cur_display_config.clk_overrides.dcfclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.scratch.cur_display_config.clk_overrides.dispclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.scratch.cur_display_config.hw.DLGRefClkFreqMHz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.scratch.new_display_config.clk_overrides.dcfclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.scratch.new_display_config.clk_overrides.dispclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.scratch.new_display_config.hw.DLGRefClkFreqMHz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.display_config.overrides.hw.dcfclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.display_config.overrides.hw.dispclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.display_config.overrides.hw.dlg_ref_clk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.dml_init.soc_bb.dcn_downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.dml_init.soc_bb.dispclk_dppclk_vco_speed_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.dml_init.soc_bb.fraction_of_urgent_bandwidth_flip_target	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.dml_init.soc_bb.fraction_of_urgent_bandwidth_nominal_target	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.dml_init.soc_bb.lower_bound_bandwidth_dchub	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.dml_init.soc_bb.phy_downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.mode_programming.dml2_instance->funcs.check_mode_supported	0,6573368814298443776
PARAM_VALUE	0	state->bw_ctx.dml2->v21.mode_programming.dml2_instance->project_id	0-4
PARAM_VALUE	0	state->bw_ctx.dml2->v21.mode_support.dml2_instance->funcs.build_mcache_programming	0,5655262704298098688
PARAM_VALUE	0	state->bw_ctx.dml2->v21.mode_support.dml2_instance->funcs.build_mode_programming	0,7150732188596219904
PARAM_VALUE	0	state->bw_ctx.dml2->v21.mode_support.dml2_instance->funcs.check_mode_supported	0,6573368814298443776
PARAM_VALUE	0	state->bw_ctx.dml2->v21.mode_support.dml2_instance->project_id	0-4
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.dml_dlg_sys_param.deepsleep_dcfclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.dml_dlg_sys_param.mem_trip_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.dml_dlg_sys_param.t_extra_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.dml_dlg_sys_param.t_mclk_wm_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.dml_dlg_sys_param.t_sr_wm_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.dml_dlg_sys_param.t_urg_wm_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.dml_dlg_sys_param.total_flip_bw	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.dml_input.clks_cfg.dcfclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.dml_input.clks_cfg.dispclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.dml_input.clks_cfg.dppclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.dml_input.clks_cfg.refclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.dml_input.clks_cfg.socclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.dml_input.dout.output_bpp	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.dml_input.dout.wb.wb_hratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.dml_input.dout.wb.wb_vratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.dml_input.pipe.dest.pixel_rate_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.dml_input.pipe.scale_ratio_depth.vinit	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.dml_input.pipe.scale_ratio_depth.vinit_c	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.pipe_dlg_param.pixel_rate_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source	0
PARAM_VALUE	0	state->dcn_bw_vars.acceptable_quality_hta_ps	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.acceptable_quality_vta_ps	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.active_dp_ps	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.active_dram_clock_change_latency_margin_c	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.active_dram_clock_change_latency_margin_y	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.average_read_bandwidth_gbyte_per_second	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.bandwidth_available_for_immediate_flip	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.block_height256_bytes_c	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.block_height256_bytes_y	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.bw_available_for_immediate_flip	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.byte_per_pix_detc	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.byte_per_pix_dety	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.critical_compression	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.critical_point	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.data_fabric_line_delivery_time_chroma	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.data_fabric_line_delivery_time_luma	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.data_pte_req_height_c	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.data_pte_req_height_y	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.data_pte_req_width_c	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.data_pte_req_width_y	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dcf_clk_deep_sleep	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dcfclk	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dcfclkv_max0p9	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dcfclkv_mid0p72	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dcfclkv_min0p65	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dcfclkv_nom0p8	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.det_buffer_size_in_kbyte	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dispclk	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dispclk_ramping_margin	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dispclk_with_ramping	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dispclk_without_ramping	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.downspreading	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dpp_output_buffer_lines_c	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dpp_output_buffer_lines_y	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dpp_output_buffer_pixels	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dppclk	-9223372036854775808.000000-9223372036854775808.000000
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PARAM_VALUE	0	state->dcn_bw_vars.rounded_up_max_swath_size_bytes_y	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.second_min_active_dram_clock_change_margin	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.smallest_vblank	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.socclk	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.sr_enter_plus_exit_time	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.sr_exit_time	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.stutter_burst_time	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.stutter_efficiency	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.stutter_efficiency_not_including_vblank	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.stutter_enter_plus_exit_watermark	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.stutter_exit_watermark	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.swath_width	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.swath_width_granularity_c	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.swath_width_granularity_y	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.t_calc	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.t_setup	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.t_wait	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.time_calc	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.time_for_fetching_meta_pte	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.time_for_fetching_row_in_vblank	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.time_for_meta_and_dpte_row_with_immediate_flip	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.time_for_meta_and_dpte_row_without_immediate_flip	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.time_for_meta_pte_with_immediate_flip	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.time_for_meta_pte_without_immediate_flip	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.time_setup	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.tot_immediate_flip_bytes	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.total_active_dpp	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.total_active_writeback	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.total_bandwidth_consumed_gbyte_per_second	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.total_data_read_bandwidth	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.total_dcc_active_dpp	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.total_number_of_active_writeback	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.total_read_bandwidth_consumed_gbyte_per_second	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.total_repeater_delay	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.total_repeater_delay_time	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.total_write_bandwidth_consumed_gbyte_per_second	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.under_scan_factor	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.urgent_extra_latency	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.urgent_latency	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.urgent_latency_support_us_chroma	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.urgent_latency_support_us_luma	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.urgent_out_of_order_return_per_channel	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.urgent_round_trip_and_out_of_order_latency	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.urgent_watermark	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.v_blank_of_min_active_dram_clock_change_margin	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.v_blank_time	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.v_init_c	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.v_init_y	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.v_startup_lines	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.vmm_page_size	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.voltage_level_with_immediate_flip	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.voltage_level_without_immediate_flip	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.wr_bandwidth	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.write_back_latency	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.writeback_chroma_buffer_size	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.writeback_chunk_size	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.writeback_dram_clock_change_latency_margin	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.writeback_dram_clock_change_watermark	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.writeback_luma_buffer_size	-9223372036854775808.000000-9223372036854775808.000000
BUF_SIZE	0	state	385448
DATA_SOURCE	0	state	r __kvmalloc_node_noprof
PREEMPT_ADD			<- disables preempt
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
HALF_LOCKED2		&dm->dc_lock

drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_state.c dc_state_create_copy() -> dc_state_release()

Type	Parameter	Key	Value
PARAM_VALUE	0	state	4096-ptr_max
PARAM_VALUE	0	state->bw_ctx.dml.ip.dcfclk_cstate_latency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.dispclk_ramp_margin_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.dsc_delay_factor_wa	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.max_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.max_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.min_prefetch_in_strobe_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.underscan_factor	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.writeback_max_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.writeback_max_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.writeback_min_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.writeback_min_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.ip.xfc_fill_bw_overhead_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.dcn_downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.dfs_vco_period_ps	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.dispclk_dppclk_vco_speed_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.dram_channel_width_bytes	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.dram_clock_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.dram_page_open_time_ns	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.dram_return_buffer_per_channel_bytes	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.dram_rw_turnaround_time_ns	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.dummy_pstate_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.fabric_datapath_to_dcn_data_return_bytes	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.fclk_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.ideal_dram_bw_after_urgent_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.mall_allocated_for_dcn_mbytes	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.max_avg_dram_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.max_avg_dram_bw_use_normal_strobe_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.max_avg_fabric_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.max_avg_sdp_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.max_vratio_pre	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.min_dcfclk	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.pct_ideal_dram_bw_after_urgent_strobe	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.pct_ideal_fabric_bw_after_urgent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.pct_ideal_sdp_bw_after_urgent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.smn_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.sr_enter_plus_exit_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.sr_enter_plus_exit_z8_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.sr_exit_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.sr_exit_z8_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.urgent_latency_adjustment_fabric_clock_component_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.urgent_latency_adjustment_fabric_clock_reference_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.urgent_latency_pixel_data_only_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.urgent_latency_pixel_mixed_with_vm_data_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.urgent_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.urgent_latency_vm_data_only_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.usr_retraining_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.writeback_dram_clock_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.writeback_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.xfc_bus_transport_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.soc.xfc_xbuf_latency_tolerance_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.AverageDCCCompressionRate	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.AverageReadBandwidth	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.AverageReadBandwidthGBytePerSecond	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.BPP	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.BandwidthAvailableForImmediateFlip	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.CriticalPoint	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.CursorBufferSize	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.CursorChunkSize	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DCFCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DCFCLKDeepSleep	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DETBufferSizeInTime	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLKDPPCLKDSCCLKDownSpreading	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLKDPPCLKVCOSpeed	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLKDelaySubtotal	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLKRampingMargin	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLKWithRamping	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLKWithRampingRoundedToDFSGranularity	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLKWithoutRamping	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLKWithoutRampingRoundedToDFSGranularity	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DISPCLK_calculated	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DPPCLKDelayCNVCCursor	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DPPCLKDelayCNVCFormater	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DPPCLKDelaySCL	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DPPCLKDelaySCLLBOnly	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DPPCLKDelaySubtotal	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DPPCLKUsingSingleDPPChroma	-1.797693e+308-1.797693e+308
PARAM_VALUE	0	state->bw_ctx.dml.vba.DPPCLKUsingSingleDPPLuma	-1.797693e+308-1.797693e+308
PARAM_VALUE	0	state->bw_ctx.dml.vba.DRAMChannelWidth	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DRAMClockChangeLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DRAMClockChangeLatencyOverride	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DRAMClockChangeWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.DRAMSpeed	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.Downspreading	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.EffectiveDETLBLinesChroma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.EffectiveDETLBLinesLuma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.EffectiveDETPlusLBLinesChroma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.EffectiveDETPlusLBLinesLuma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.EffectiveFECOverhead	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.ExtraLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.FCLKChangeLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.FECOverhead	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.FabricAndDRAMBandwidth	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.FabricClock	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.FabricDatapathToDCNDataReturn	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.FinalDRAMClockChangeLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.FinalFillLevel	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.FinalFillMargin	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.FractionOfUrgentBandwidth	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.FractionOfUrgentBandwidthImmediateFlip	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.FrameTimeForMinFullDETBufferingTime	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.GPUVMMinPageSize	-9.223372e+18-9.223372e+18
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PARAM_VALUE	0	state->bw_ctx.dml.vba.LastPixelOfLineExtraWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.LinesInDETChroma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.LinesInDETLuma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.LinesToFinishSwathTransferStutterCriticalPlane	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaxDCHUBToPSCLThroughput	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaxDispclkRoundedDownToDFSGranularity	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaxDispclkRoundedToDFSGranularity	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaxDppclkRoundedDownToDFSGranularity	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaxHSCLRatio	-9.223372e+18-9.223372e+18
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PARAM_VALUE	0	state->bw_ctx.dml.vba.MaxTotalVActiveRDBandwidth	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaxVRatioPre	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaxVSCLRatio	-9.223372e+18-9.223372e+18
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PARAM_VALUE	0	state->bw_ctx.dml.vba.MaximumReadBandwidthWithoutPrefetch	-9.223372e+18-9.223372e+18
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PARAM_VALUE	0	state->bw_ctx.dml.vba.MaximumSwathWidthInLineBufferChroma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaximumSwathWidthInLineBufferLuma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MaximumSwathWidthSupport	-9.223372e+18-9.223372e+18
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PARAM_VALUE	0	state->bw_ctx.dml.vba.MinActiveDRAMClockChangeMargin	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.MinActiveFCLKChangeLatencySupported	-9.223372e+18-9.223372e+18
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PARAM_VALUE	0	state->bw_ctx.dml.vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencySTROBE	-9.223372e+18-9.223372e+18
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PARAM_VALUE	0	state->bw_ctx.dml.vba.PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency	-9.223372e+18-9.223372e+18
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PARAM_VALUE	0	state->bw_ctx.dml.vba.PlaneRequiredDISPCLKWithODMCombine4To1	-9.223372e+18-9.223372e+18
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PARAM_VALUE	0	state->bw_ctx.dml.vba.Z8StutterEfficiencyNotIncludingVBlank	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.Z8StutterEfficiencyNotIncludingVBlankBestCase	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.Z8StutterEnterPlusExitWatermark	-9.223372e+18-9.223372e+18
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PARAM_VALUE	0	state->bw_ctx.dml.vba.bpp	-9.223372e+18-9.223372e+18
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PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.downspread_percent	-9.223372e+18-9.223372e+18
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PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.dummy_pstate_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.fabric_datapath_to_dcn_data_return_bytes	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.fclk_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.ideal_dram_bw_after_urgent_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.mall_allocated_for_dcn_mbytes	-9.223372e+18-9.223372e+18
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PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.max_avg_dram_bw_use_normal_strobe_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.max_avg_fabric_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.max_avg_sdp_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.max_vratio_pre	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.min_dcfclk	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.pct_ideal_dram_bw_after_urgent_strobe	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.pct_ideal_fabric_bw_after_urgent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.pct_ideal_sdp_bw_after_urgent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.smn_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.sr_enter_plus_exit_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.sr_enter_plus_exit_z8_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.sr_exit_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.sr_exit_z8_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.urgent_latency_adjustment_fabric_clock_component_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.urgent_latency_adjustment_fabric_clock_reference_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.urgent_latency_pixel_data_only_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.urgent_latency_pixel_mixed_with_vm_data_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.urgent_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.urgent_latency_vm_data_only_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.usr_retraining_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.writeback_dram_clock_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.writeback_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.xfc_bus_transport_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.soc.xfc_xbuf_latency_tolerance_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.total_dcn_read_bw_with_flip	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml.vba.total_dcn_read_bw_with_flip_no_urgent_burst	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->architecture	0-4294967295
PARAM_VALUE	0	state->bw_ctx.dml2->config.bbox_overrides.dchub_refclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->config.bbox_overrides.disp_pll_vco_speed_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->config.bbox_overrides.dprefclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->config.bbox_overrides.dram_clock_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->config.bbox_overrides.fclk_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->config.bbox_overrides.sr_enter_plus_exit_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->config.bbox_overrides.sr_enter_plus_exit_z8_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->config.bbox_overrides.sr_exit_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->config.bbox_overrides.sr_exit_z8_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->config.bbox_overrides.urgent_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->config.bbox_overrides.xtalclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ip.dispclk_ramp_margin_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ip.max_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ip.max_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ip.writeback_max_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ip.writeback_max_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ip.writeback_min_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ip.writeback_min_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.BandwidthAvailableForImmediateFlip	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.DCFCLKDeepSleep	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Dcfclk	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Dispclk	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Dispclk_calculated	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.FractionOfUrgentBandwidth	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.FractionOfUrgentBandwidthImmediateFlip	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.GlobalDPPCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.MaxActiveFCLKChangeLatencySupported	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.StutterEfficiency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.StutterEfficiencyNotIncludingVBlank	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.StutterPeriod	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.StutterPeriodBestCase	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.TCalc	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.TotalDataReadBandwidth	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.UrgentExtraLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.UrgentLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.UrgentLatencyWithUSRRetraining	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Watermark.DRAMClockChangeWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Watermark.FCLKChangeWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Watermark.StutterEnterPlusExitWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Watermark.StutterExitWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Watermark.USRRetrainingWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Watermark.UrgentWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Watermark.WritebackDRAMClockChangeWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Watermark.WritebackFCLKChangeWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Watermark.WritebackUrgentWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Watermark.Z8StutterEnterPlusExitWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Watermark.Z8StutterExitWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.WritebackDISPCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Z8StutterEfficiency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Z8StutterEfficiencyBestCase	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.Z8StutterEfficiencyNotIncludingVBlank	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.non_urgent_total_dcn_read_bw_with_flip	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.total_dcn_read_bw_with_flip	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.mp.total_dcn_read_bw_with_flip_no_urgent_burst	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.BandwidthAvailableForImmediateFlip	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.DCFCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.DRAMSpeed	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.ExtraLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.FabricClock	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.GlobalDPPCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.MaximumSwathWidthInLineBufferChroma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.MaximumSwathWidthInLineBufferLuma	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.ReturnBW	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.ReturnDRAMBW	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.SOCCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.TWait	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.TimeCalc	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.UrgLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.WritebackRequiredDISPCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.cache_display_cfg.clk_overrides.dcfclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.cache_display_cfg.clk_overrides.dispclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.cache_display_cfg.hw.DLGRefClkFreqMHz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.ip.dispclk_ramp_margin_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.ip.max_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.ip.max_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.ip.writeback_max_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.ip.writeback_max_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.ip.writeback_min_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.ip.writeback_min_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.dcfclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.dispclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.dppclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.dram_clock_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.dram_speed_mts	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.dscclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.dtbclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.fabricclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.fclk_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.g6_temp_read_blackout_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.phyclk_d18_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.phyclk_d32_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.phyclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.socclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.sr_enter_plus_exit_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.sr_enter_plus_exit_z8_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.sr_exit_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.sr_exit_z8_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.urgent_latency_pixel_data_only_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.urgent_latency_vm_data_only_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.usr_retraining_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.max_state.writeback_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.amclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.dcn_downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.dispclk_dppclk_vco_speed_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.dprefclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.max_avg_dram_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.max_avg_fabric_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.max_avg_sdp_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.pcierefclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.pct_ideal_dram_bw_after_urgent_strobe	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.pct_ideal_dram_bw_after_urgent_vm_only	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.pct_ideal_fabric_bw_after_urgent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.pct_ideal_sdp_bw_after_urgent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.phy_downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.refclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.smn_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.soc.xtalclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.dcfclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.dispclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.dppclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.dram_clock_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.dram_speed_mts	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.dscclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.dtbclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.fabricclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.fclk_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.g6_temp_read_blackout_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.phyclk_d18_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.phyclk_d32_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.phyclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.socclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.sr_enter_plus_exit_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.sr_enter_plus_exit_z8_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.sr_exit_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.sr_exit_z8_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.urgent_latency_pixel_data_only_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.urgent_latency_vm_data_only_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.usr_retraining_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.ms.state.writeback_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Tdmbf	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_locals.Tdmec	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_params.TCalc	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.scratch.CalculatePrefetchSchedule_params.TWait	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.scratch.UseMinimumDCFCLK_locals.DPTEBandwidth	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.scratch.UseMinimumDCFCLK_locals.MinimumTWait	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.scratch.UseMinimumDCFCLK_params.DCFCLKPerState	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.scratch.UseMinimumDCFCLK_params.UrgLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.amclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.dcn_downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.dispclk_dppclk_vco_speed_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.dprefclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.max_avg_dram_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.max_avg_dram_bw_use_normal_strobe_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.max_avg_fabric_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.max_avg_sdp_bw_use_normal_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.pcierefclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.pct_ideal_dram_bw_after_urgent_pixel_only	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.pct_ideal_dram_bw_after_urgent_strobe	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.pct_ideal_dram_bw_after_urgent_vm_only	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.pct_ideal_fabric_bw_after_urgent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.pct_ideal_sdp_bw_after_urgent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.phy_downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.refclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.smn_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.svp_prefetch_pct_ideal_sdp_bw_after_urgent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.dml_core_ctx.soc.xtalclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.scratch.cur_display_config.clk_overrides.dcfclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.scratch.cur_display_config.clk_overrides.dispclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.scratch.cur_display_config.hw.DLGRefClkFreqMHz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.scratch.new_display_config.clk_overrides.dcfclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.scratch.new_display_config.clk_overrides.dispclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v20.scratch.new_display_config.hw.DLGRefClkFreqMHz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.display_config.overrides.hw.dcfclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.display_config.overrides.hw.dispclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.display_config.overrides.hw.dlg_ref_clk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.dml_init.soc_bb.dcn_downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.dml_init.soc_bb.dispclk_dppclk_vco_speed_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.dml_init.soc_bb.fraction_of_urgent_bandwidth_flip_target	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.dml_init.soc_bb.fraction_of_urgent_bandwidth_nominal_target	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.dml_init.soc_bb.lower_bound_bandwidth_dchub	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.dml_init.soc_bb.phy_downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.mode_programming.dml2_instance->project_id	0-4294967295
PARAM_VALUE	0	state->bw_ctx.dml2->v21.mode_support.dml2_instance->project_id	0-4294967295
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.dml_dlg_sys_param.deepsleep_dcfclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.dml_dlg_sys_param.mem_trip_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.dml_dlg_sys_param.t_extra_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.dml_dlg_sys_param.t_mclk_wm_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.dml_dlg_sys_param.t_sr_wm_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.dml_dlg_sys_param.t_urg_wm_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.dml_dlg_sys_param.total_flip_bw	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.dml_input.clks_cfg.dcfclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.dml_input.clks_cfg.dispclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.dml_input.clks_cfg.dppclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.dml_input.clks_cfg.refclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.dml_input.clks_cfg.socclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.dml_input.dout.output_bpp	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.dml_input.dout.wb.wb_hratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.dml_input.dout.wb.wb_vratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.dml_input.pipe.dest.pixel_rate_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.dml_input.pipe.scale_ratio_depth.vinit	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.dml_input.pipe.scale_ratio_depth.vinit_c	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2->v21.scratch.temp_pipe.pipe_dlg_param.pixel_rate_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source	0,4096-ptr_max
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->config.bbox_overrides.dchub_refclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->config.bbox_overrides.disp_pll_vco_speed_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->config.bbox_overrides.dprefclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->config.bbox_overrides.fclk_change_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->config.bbox_overrides.sr_exit_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->config.bbox_overrides.sr_exit_z8_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->config.bbox_overrides.urgent_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->config.bbox_overrides.xtalclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ip.dispclk_ramp_margin_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ip.max_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ip.max_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ip.writeback_max_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ip.writeback_max_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ip.writeback_min_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ip.writeback_min_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.mp.DCFCLKDeepSleep	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.mp.Dcfclk	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.mp.Dispclk	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.mp.Dispclk_calculated	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.mp.FractionOfUrgentBandwidth	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.mp.GlobalDPPCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.mp.StutterEfficiency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.mp.StutterPeriod	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.mp.StutterPeriodBestCase	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.mp.TCalc	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.mp.TotalDataReadBandwidth	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.mp.UrgentExtraLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.mp.UrgentLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.mp.Watermark.UrgentWatermark	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.mp.WritebackDISPCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.mp.Z8StutterEfficiency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.mp.Z8StutterEfficiencyBestCase	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.mp.total_dcn_read_bw_with_flip	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.DCFCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.DRAMSpeed	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.ExtraLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.FabricClock	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.GlobalDPPCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.ReturnBW	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.ReturnDRAMBW	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.SOCCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.TWait	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.TimeCalc	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.UrgLatency	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.WritebackRequiredDISPCLK	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.ip.max_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.ip.max_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.ip.writeback_max_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.ip.writeback_max_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.ip.writeback_min_hscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.ip.writeback_min_vscl_ratio	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.max_state.dcfclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.max_state.dispclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.max_state.dppclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.max_state.dram_speed_mts	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.max_state.dscclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.max_state.dtbclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.max_state.fabricclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.max_state.phyclk_d18_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.max_state.phyclk_d32_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.max_state.phyclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.max_state.socclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.max_state.sr_exit_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.soc.amclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.soc.dcn_downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.soc.dprefclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.soc.pcierefclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.soc.phy_downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.soc.refclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.soc.smn_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.soc.xtalclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.state.dcfclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.state.dispclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.state.dppclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.state.dram_speed_mts	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.state.dscclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.state.dtbclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.state.fabricclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.state.phyclk_d18_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.state.phyclk_d32_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.state.phyclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.state.socclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.state.sr_exit_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.state.sr_exit_z8_time_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.ms.state.writeback_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.soc.amclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.soc.dcn_downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.soc.dprefclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.soc.pcierefclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.soc.phy_downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.soc.refclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.soc.smn_latency_us	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v20.dml_core_ctx.soc.xtalclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v21.display_config.overrides.hw.dcfclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v21.display_config.overrides.hw.dispclk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v21.display_config.overrides.hw.dlg_ref_clk_mhz	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v21.dml_init.soc_bb.dcn_downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v21.dml_init.soc_bb.lower_bound_bandwidth_dchub	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v21.dml_init.soc_bb.phy_downspread_percent	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v21.mode_programming.dml2_instance->project_id	0-4
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v21.mode_support.dml2_instance->project_id	0-4
PARAM_VALUE	0	state->bw_ctx.dml2_dc_power_source->v21.scratch.temp_pipe.dml_input.dout.output_bpp	-9.223372e+18-9.223372e+18
PARAM_VALUE	0	state->dcn_bw_vars.acceptable_quality_hta_ps	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.acceptable_quality_vta_ps	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.active_dp_ps	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.active_dram_clock_change_latency_margin_c	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.active_dram_clock_change_latency_margin_y	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.average_read_bandwidth_gbyte_per_second	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.bandwidth_available_for_immediate_flip	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.block_height256_bytes_c	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.block_height256_bytes_y	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.bw_available_for_immediate_flip	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.byte_per_pix_detc	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.byte_per_pix_dety	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.critical_compression	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.critical_point	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.data_fabric_line_delivery_time_chroma	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.data_fabric_line_delivery_time_luma	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.data_pte_req_height_c	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.data_pte_req_height_y	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.data_pte_req_width_c	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.data_pte_req_width_y	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dcf_clk_deep_sleep	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dcfclk	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dcfclkv_max0p9	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dcfclkv_mid0p72	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dcfclkv_min0p65	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dcfclkv_nom0p8	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.det_buffer_size_in_kbyte	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dispclk	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dispclk_ramping_margin	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dispclk_with_ramping	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dispclk_without_ramping	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.downspreading	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dpp_output_buffer_lines_c	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dpp_output_buffer_lines_y	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dpp_output_buffer_pixels	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dppclk	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dppclk_using_single_dpp	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dppclk_using_single_dpp_chroma	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dppclk_using_single_dpp_luma	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dppopp_buffering_c	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dppopp_buffering_y	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dpte_bytes_per_row_c	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dpte_bytes_per_row_y	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dram_clock_change_latency	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dram_clock_change_margin	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dram_clock_change_support	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dram_clock_change_watermark	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dst_x_after_scaler	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dst_y_after_scaler	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dstx_after_scaler	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.dsty_after_scaler	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.effective_det_plus_lb_lines_chroma	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.effective_det_plus_lb_lines_luma	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.effective_detlb_lines_chroma	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.effective_detlb_lines_luma	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.effective_lb_latency_hiding_c	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.effective_lb_latency_hiding_source_lines_chroma	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.effective_lb_latency_hiding_source_lines_luma	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.effective_lb_latency_hiding_y	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.extra_latency	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.fabric_and_dram_bandwidth	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.fabric_and_dram_bandwidth_vmax0p9	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.fabric_and_dram_bandwidth_vmid0p72	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.fabric_and_dram_bandwidth_vmin0p65	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.fabric_and_dram_bandwidth_vnom0p8	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.frame_time_for_min_full_det_buffering_time	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.frequency	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.header	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.header_line	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.last_pixel_of_line_extra_watermark	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.lb_latency_hiding_source_lines_c	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.lb_latency_hiding_source_lines_y	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.line_buffer_fixed_bpp	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.line_buffer_size	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.line_times_to_request_prefetch_pixel_data_with_immediate_flip	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.line_times_to_request_prefetch_pixel_data_without_immediate_flip	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.lines_in_det_chroma	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.lines_in_det_luma	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.lines_to_request_prefetch_pixel_data	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.macro_tile_block_height_c	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.macro_tile_block_height_y	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.macro_tile_block_size_bytes_c	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.macro_tile_block_size_bytes_y	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.macro_tile_block_width_c	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.macro_tile_height_c	-9223372036854775808.000000-9223372036854775808.000000
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PARAM_VALUE	0	state->dcn_bw_vars.write_back_latency	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.writeback_chroma_buffer_size	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.writeback_chunk_size	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.writeback_dram_clock_change_latency_margin	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.writeback_dram_clock_change_watermark	-9223372036854775808.000000-9223372036854775808.000000
PARAM_VALUE	0	state->dcn_bw_vars.writeback_luma_buffer_size	-9223372036854775808.000000-9223372036854775808.000000
BUF_SIZE	0	state	385448
DATA_SOURCE	0	state	r __kvmalloc_node_noprof
PREEMPT_ADD			<- disables preempt
RX_PATH
TASK_NOT_RUNNING
NOCHECK_CALL
HALF_LOCKED2		&dm->dc_lock