Defined in 1 files as a prototype:
Defined in 1 files as a function:
Referenced in 3 files:
- drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c, line 2464
- drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
- drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c, line 1835
Smatch caller information:
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn20/dcn20_hwseq.c dcn20_optimize_bandwidth() -> dc_dmub_srv_p_state_delegate()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dc | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->clk_mgr | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->current_state->bw_ctx.dml.vba.DPPCLKUsingSingleDPPChroma | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | dc->current_state->bw_ctx.dml.vba.DPPCLKUsingSingleDPPLuma | -1.797693e+308-1.797693e+308 |
| PARAM_VALUE | 0 | dc->res_pool | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->funcs->prepare_mcache_programming | 0,804463396097511424,929829862513430528,8759039014133256192 |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->program_compbuf_size | 0,2648268354096648192,5203554456492613632,8471972876937388032 |
| PARAM_VALUE | 0 | dc->res_pool->res_cap->num_dsc | 0,2-6 |
| PARAM_VALUE | 1 | should_manage_pstate | 1 |
| PARAM_VALUE | 2 | context | 4096-ptr_max |
| PARAM_VALUE | 2 | context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching | 1 |
| BUF_SIZE | 2 | context | (-1),370336 |
| BUF_SIZE | 2 | context | (-1),370336 |
| CAPPED_DATA | 0 | dc->res_pool->pipe_count | 1 |
| DATA_SOURCE | 0 | dc | $0 |
| DATA_SOURCE | 2 | context | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn32/dcn32_hwseq.c dcn32_prepare_bandwidth() -> dc_dmub_srv_p_state_delegate()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dc | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->clk_mgr | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->clk_mgr->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->clk_mgr->funcs->update_clocks | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->hubbub | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->program_watermarks | 4096-ptr_max |
| PARAM_VALUE | 1 | should_manage_pstate | 0 |
| PARAM_VALUE | 2 | context | 4096-ptr_max |
| CAPPED_DATA | 0 | dc->res_pool->pipe_count | 1 |
| DATA_SOURCE | 0 | dc | $0 |
| DATA_SOURCE | 2 | context | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn30/dcn30_hwseq.c dcn30_hardware_release() -> dc_dmub_srv_p_state_delegate()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dc | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->current_state | 0,4096-ptr_max |
| PARAM_VALUE | 0 | dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down | 1 |
| PARAM_VALUE | 0 | dc->hwss.hardware_release | 1-u64max |
| PARAM_VALUE | 1 | should_manage_pstate | 0 |
| PARAM_VALUE | 2 | context | 0 |
| DATA_SOURCE | 0 | dc | $0 |
| NOCHECK_CALL |
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn30/dcn30_hwseq.c dcn30_prepare_bandwidth() -> dc_dmub_srv_p_state_delegate()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | dc | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->clk_mgr | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->clk_mgr->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->clk_mgr->funcs->update_clocks | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->hubbub | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs | 4096-ptr_max |
| PARAM_VALUE | 0 | dc->res_pool->hubbub->funcs->program_watermarks | 4096-ptr_max |
| PARAM_VALUE | 1 | should_manage_pstate | 0 |
| PARAM_VALUE | 2 | context | 4096-ptr_max |
| CAPPED_DATA | 0 | dc->res_pool->pipe_count | 1 |
| DATA_SOURCE | 0 | dc | $0 |
| DATA_SOURCE | 2 | context | $1 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL |