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Defined in 1 files as a function:

Referenced in 1 files:

Smatch caller information:

drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_clock_source.c dce110_clk_src_construct() -> calc_pll_max_vco_construct()

Type Parameter Key Value
PARAM_VALUE 0 clk_src 4096-ptr_max
PARAM_VALUE 0 clk_src->base.ctx 4096-ptr_max
PARAM_VALUE 0 clk_src->base.ctx->asic_id.chip_id 0-u16max
PARAM_VALUE 0 clk_src->base.ctx->asic_id.pci_revision_id 0-255
PARAM_VALUE 0 clk_src->base.ctx->clk_reg_offsets 4096-ptr_max
PARAM_VALUE 0 clk_src->base.ctx->cp_psp.funcs.enable_assr 0,2165108512918093824
PARAM_VALUE 0 clk_src->base.ctx->cp_psp.funcs.update_stream_config 0,2588822157271744512
PARAM_VALUE 0 clk_src->base.ctx->created_bios 1
PARAM_VALUE 0 clk_src->base.ctx->dc 4096-ptr_max
PARAM_VALUE 0 clk_src->base.ctx->dc_bios 4096-ptr_max
PARAM_VALUE 0 clk_src->base.ctx->dc_edp_id_count 0
PARAM_VALUE 0 clk_src->base.ctx->dc_sink_id_count 0
PARAM_VALUE 0 clk_src->base.ctx->dc_stream_id_count 0
PARAM_VALUE 0 clk_src->base.ctx->dce_version 0-11,13-33
PARAM_VALUE 0 clk_src->base.ctx->dcn_reg_offsets 4096-ptr_max
PARAM_VALUE 0 clk_src->base.ctx->driver_context 4096-ptr_max
PARAM_VALUE 0 clk_src->base.ctx->gpio_service 4096-ptr_max
PARAM_VALUE 0 clk_src->base.ctx->logger 4096-ptr_max
PARAM_VALUE 0 clk_src->base.ctx->nbio_reg_offsets 4096-ptr_max
PARAM_VALUE 0 clk_src->base.ctx->perf_trace 4096-ptr_max
PARAM_VALUE 0 clk_src->base.funcs 1555285616259411968
PARAM_VALUE 0 clk_src->base.id 1-3
PARAM_VALUE 0 clk_src->bios 4096-ptr_max
PARAM_VALUE 0 clk_src->bios->fw_info_valid 1
PARAM_VALUE 0 clk_src->bios->regs 348429412772642816,3249662903216037888,5786701193721225216,8642778718746595328
PARAM_VALUE 0 clk_src->cs_mask 4346225338794291200,6227021662886178816,8001320132450648064,8440148017990684672
PARAM_VALUE 0 clk_src->cs_mask->PLL_POST_DIV_PIXCLK 0,127
PARAM_VALUE 0 clk_src->cs_mask->PLL_REF_DIV 0,1023
PARAM_VALUE 0 clk_src->cs_shift 781084288015626240,2806140636255617024,2842867926561308672,6400199634142052352
PARAM_VALUE 0 clk_src->regs 0,4096-ptr_max
PARAM_VALUE 1 calc_pll_cs 4096-ptr_max
PARAM_VALUE 2 init_data 7524892088899788800
PARAM_VALUE 2 init_data->bp 4096-ptr_max
PARAM_VALUE 2 init_data->ctx 4096-ptr_max
PARAM_VALUE 2 init_data->max_override_input_pxl_clk_pll_freq_khz 0
PARAM_VALUE 2 init_data->max_pix_clk_pll_post_divider 0,127
PARAM_VALUE 2 init_data->max_pll_ref_divider 0,1023
PARAM_VALUE 2 init_data->min_override_input_pxl_clk_pll_freq_khz 0
PARAM_VALUE 2 init_data->min_pix_clk_pll_post_divider 1
PARAM_VALUE 2 init_data->min_pll_ref_divider 1
PARAM_VALUE 2 init_data->num_fract_fb_divider_decimal_point 6
PARAM_VALUE 2 init_data->num_fract_fb_divider_decimal_point_precision 6
BUF_SIZE 0 clk_src 256
BUF_SIZE 0 clk_src->base.funcs 40
BUF_SIZE 0 clk_src->regs (-1),176,264
DATA_SOURCE 0 clk_src $0
BIT_INFO 0 clk_src->base.id 0x0,0x7
RX_PATH
TASK_NOT_RUNNING
NO_OVERFLOW_SIMPLE 0 clk_src->dp_ss_params_cnt
NO_OVERFLOW_SIMPLE 0 clk_src->dvi_ss_params_cnt
NO_OVERFLOW_SIMPLE 0 clk_src->hdmi_ss_params_cnt
NO_OVERFLOW_SIMPLE 0 clk_src->lvds_ss_params_cnt

drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_clock_source.c dce110_clk_src_construct() -> calc_pll_max_vco_construct()

Type Parameter Key Value
PARAM_VALUE 0 clk_src 4096-ptr_max
PARAM_VALUE 0 clk_src->base.ctx 4096-ptr_max
PARAM_VALUE 0 clk_src->base.ctx->asic_id.chip_id 0-u16max
PARAM_VALUE 0 clk_src->base.ctx->asic_id.pci_revision_id 0-255
PARAM_VALUE 0 clk_src->base.ctx->clk_reg_offsets 4096-ptr_max
PARAM_VALUE 0 clk_src->base.ctx->cp_psp.funcs.enable_assr 0,2165108512918093824
PARAM_VALUE 0 clk_src->base.ctx->cp_psp.funcs.update_stream_config 0,2588822157271744512
PARAM_VALUE 0 clk_src->base.ctx->created_bios 1
PARAM_VALUE 0 clk_src->base.ctx->dc 4096-ptr_max
PARAM_VALUE 0 clk_src->base.ctx->dc_bios 4096-ptr_max
PARAM_VALUE 0 clk_src->base.ctx->dc_edp_id_count 0
PARAM_VALUE 0 clk_src->base.ctx->dc_sink_id_count 0
PARAM_VALUE 0 clk_src->base.ctx->dc_stream_id_count 0
PARAM_VALUE 0 clk_src->base.ctx->dce_version 0-11,13-33
PARAM_VALUE 0 clk_src->base.ctx->dcn_reg_offsets 4096-ptr_max
PARAM_VALUE 0 clk_src->base.ctx->driver_context 4096-ptr_max
PARAM_VALUE 0 clk_src->base.ctx->gpio_service 4096-ptr_max
PARAM_VALUE 0 clk_src->base.ctx->logger 4096-ptr_max
PARAM_VALUE 0 clk_src->base.ctx->nbio_reg_offsets 4096-ptr_max
PARAM_VALUE 0 clk_src->base.ctx->perf_trace 4096-ptr_max
PARAM_VALUE 0 clk_src->base.funcs 1555285616259411968
PARAM_VALUE 0 clk_src->base.id 1-3
PARAM_VALUE 0 clk_src->bios 4096-ptr_max
PARAM_VALUE 0 clk_src->bios->fw_info_valid 1
PARAM_VALUE 0 clk_src->bios->regs 348429412772642816,3249662903216037888,5786701193721225216,8642778718746595328
PARAM_VALUE 0 clk_src->calc_pll.ctx 4096-ptr_max
PARAM_VALUE 0 clk_src->calc_pll.fract_fb_divider_decimal_points_num 6
PARAM_VALUE 0 clk_src->calc_pll.fract_fb_divider_factor 10,100
PARAM_VALUE 0 clk_src->calc_pll.fract_fb_divider_precision 6
PARAM_VALUE 0 clk_src->calc_pll.fract_fb_divider_precision_factor 1,10,100
PARAM_VALUE 0 clk_src->calc_pll.max_pix_clock_pll_post_divider 0,127
PARAM_VALUE 0 clk_src->calc_pll.max_pll_ref_divider 0,1023
PARAM_VALUE 0 clk_src->calc_pll.min_pix_clock_pll_post_divider 1
PARAM_VALUE 0 clk_src->calc_pll.min_pll_ref_divider 1
PARAM_VALUE 0 clk_src->cs_mask 4346225338794291200,6227021662886178816,8001320132450648064,8440148017990684672
PARAM_VALUE 0 clk_src->cs_mask->PLL_POST_DIV_PIXCLK 0,127
PARAM_VALUE 0 clk_src->cs_mask->PLL_REF_DIV 0,1023
PARAM_VALUE 0 clk_src->cs_shift 781084288015626240,2806140636255617024,2842867926561308672,6400199634142052352
PARAM_VALUE 0 clk_src->regs 0,4096-ptr_max
PARAM_VALUE 1 calc_pll_cs 4096-ptr_max
PARAM_VALUE 2 init_data 6476382936128827392
PARAM_VALUE 2 init_data->bp 4096-ptr_max
PARAM_VALUE 2 init_data->ctx 4096-ptr_max
PARAM_VALUE 2 init_data->max_pix_clk_pll_post_divider 0,127
PARAM_VALUE 2 init_data->max_pll_ref_divider 0,1023
PARAM_VALUE 2 init_data->min_pix_clk_pll_post_divider 1
PARAM_VALUE 2 init_data->min_pll_ref_divider 1
PARAM_VALUE 2 init_data->num_fract_fb_divider_decimal_point 6
PARAM_VALUE 2 init_data->num_fract_fb_divider_decimal_point_precision 6
BUF_SIZE 0 clk_src 256
BUF_SIZE 0 clk_src->base.funcs 40
BUF_SIZE 0 clk_src->regs (-1),176,264
DATA_SOURCE 0 clk_src $0
BIT_INFO 0 clk_src->base.id 0x0,0x7
RX_PATH
TASK_NOT_RUNNING
NO_OVERFLOW_SIMPLE 0 clk_src->dp_ss_params_cnt
NO_OVERFLOW_SIMPLE 0 clk_src->dvi_ss_params_cnt
NO_OVERFLOW_SIMPLE 0 clk_src->hdmi_ss_params_cnt
NO_OVERFLOW_SIMPLE 0 clk_src->lvds_ss_params_cnt