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Defined in 1 files as a function:

Referenced in 1 files:

Smatch caller information:

drivers/gpu/drm/i915/display/intel_dpll_mgr.c bxt_ddi_hdmi_set_dpll_hw_state() -> bxt_ddi_pll_get_freq()

Type Parameter Key Value
PARAM_VALUE 1 pll 0
PARAM_VALUE 2 dpll_hw_state 4096-ptr_max
PARAM_VALUE 2 dpll_hw_state->bxt.ebb0 0-u16max
PARAM_VALUE 2 dpll_hw_state->bxt.ebb4 8192
PARAM_VALUE 2 dpll_hw_state->bxt.pcsdw12 66,68,71,77,88
PARAM_VALUE 2 dpll_hw_state->bxt.pll0 0-255
PARAM_VALUE 2 dpll_hw_state->bxt.pll1 0,256-3840
PARAM_VALUE 2 dpll_hw_state->bxt.pll10 134217728,134218752-134233088
PARAM_VALUE 2 dpll_hw_state->bxt.pll2 0-4194303
PARAM_VALUE 2 dpll_hw_state->bxt.pll3 65536
PARAM_VALUE 2 dpll_hw_state->bxt.pll8 0-1023
PARAM_VALUE 2 dpll_hw_state->bxt.pll9 0,2-14
RX_PATH
TASK_NOT_RUNNING

drivers/gpu/drm/i915/display/intel_dpll_mgr.c intel_dpll_get_freq() -> (struct intel_dpll_funcs)->get_freq()

Type Parameter Key Value
PARAM_VALUE 1 pll 4096-ptr_max
PARAM_VALUE 1 pll->index 0-8
PARAM_VALUE 1 pll->info 4096-ptr_max
PARAM_VALUE 1 pll->info->funcs 4096-ptr_max
PARAM_VALUE 1 pll->info->funcs->get_freq 1-u64max
PARAM_VALUE 1 pll->info->id 0-8
PARAM_VALUE 2 dpll_hw_state 4096-ptr_max
DATA_SOURCE 0 display $0
DATA_SOURCE 1 pll $1
DATA_SOURCE 2 dpll_hw_state $2
CONTAINER 1 -24-8-96+0 $(-1)
RX_PATH
TASK_NOT_RUNNING
HOST_DATA 2 dpll_hw_state->bxt.ebb0 0,256-65280[c]
HOST_DATA 2 dpll_hw_state->bxt.ebb4 0,8192[c]
HOST_DATA 2 dpll_hw_state->bxt.pcsdw12 0-95[c]
HOST_DATA 2 dpll_hw_state->bxt.pll0 0-255[c]
HOST_DATA 2 dpll_hw_state->bxt.pll1 0,256-3840[c]
HOST_DATA 2 dpll_hw_state->bxt.pll10 0,1024-134233088[c]
HOST_DATA 2 dpll_hw_state->bxt.pll2 0-4194303[c]
HOST_DATA 2 dpll_hw_state->bxt.pll3 0,65536[c]
HOST_DATA 2 dpll_hw_state->bxt.pll6 0-466703[c]
HOST_DATA 2 dpll_hw_state->bxt.pll8 0-1023[c]
HOST_DATA 2 dpll_hw_state->bxt.pll9 0,2-14[c]
HOST_DATA 2 dpll_hw_state->cx0pll.ssc_enabled 0-1
HOST_DATA 2 dpll_hw_state->hsw.spll 0-u32max
HOST_DATA 2 dpll_hw_state->hsw.wrpll 0-u32max
HOST_DATA 2 dpll_hw_state->i9xx.dpll 0-u32max
HOST_DATA 2 dpll_hw_state->i9xx.dpll_md 0-u32max
HOST_DATA 2 dpll_hw_state->i9xx.fp0 0-u32max
HOST_DATA 2 dpll_hw_state->i9xx.fp1 0-u32max
HOST_DATA 2 dpll_hw_state->icl.cfgcr0 0-u32max
HOST_DATA 2 dpll_hw_state->icl.cfgcr1 0-u32max
HOST_DATA 2 dpll_hw_state->icl.div0 0,33554432-234881024[c]
HOST_DATA 2 dpll_hw_state->icl.mg_clktop2_coreclkctl1 0,256-65280[c]
HOST_DATA 2 dpll_hw_state->icl.mg_clktop2_hsclkctl 0,256-130816[c]
HOST_DATA 2 dpll_hw_state->icl.mg_pll_bias 0-u32max[c]
HOST_DATA 2 dpll_hw_state->icl.mg_pll_div0 0-u32max
HOST_DATA 2 dpll_hw_state->icl.mg_pll_div1 0-u32max
HOST_DATA 2 dpll_hw_state->icl.mg_pll_frac_lock 0-u32max
HOST_DATA 2 dpll_hw_state->icl.mg_pll_lf 0-u32max
HOST_DATA 2 dpll_hw_state->icl.mg_pll_ssc 0-u32max
HOST_DATA 2 dpll_hw_state->icl.mg_pll_tdc_coldst_bias 0-u32max[c]
HOST_DATA 2 dpll_hw_state->icl.mg_refclkin_ctl 0,256-1792[c]
HOST_DATA 2 dpll_hw_state->skl.cfgcr1 0-u32max
HOST_DATA 2 dpll_hw_state->skl.cfgcr2 0-u32max