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Documented in 1 files:

Defined in 1 files as a prototype:

Defined in 1 files as a function:

Referenced in 2 files:

Smatch caller information:

drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c amdgpu_ras_eeprom_check_and_recover() -> amdgpu_ras_eeprom_reset_table()

Type Parameter Key Value
PARAM_VALUE 0 control 4096-ptr_max
PARAM_VALUE 0 control->is_eeprom_valid 1
BUF_SIZE 0 control 480
RX_PATH
TASK_NOT_RUNNING
HALF_LOCKED2 &dev->mutex

drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c amdgpu_ras_eeprom_init() -> amdgpu_ras_eeprom_reset_table()

Type Parameter Key Value
PARAM_VALUE 0 control 4096-ptr_max
PARAM_VALUE 0 control->i2c_address 0,65536-196608,262144
PARAM_VALUE 0 control->ras_header_offset 0
PARAM_VALUE 0 control->ras_info_offset 20
PARAM_VALUE 0 control->ras_tbl_mutex.dep_map->name 0-255
PARAM_VALUE 0 control->ras_tbl_mutex.first_waiter 0
PARAM_VALUE 0 control->ras_tbl_mutex.magic 4096-ptr_max
PARAM_VALUE 0 control->ras_tbl_mutex.osq.tail.counter 0
PARAM_VALUE 0 control->ras_tbl_mutex.owner.counter 0
PARAM_VALUE 0 control->tbl_hdr.header 0-1095582801,1095582803-1111573574,1111573576-u32max
BUF_SIZE 0 control 480
DATA_SOURCE 0 control $0

drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c amdgpu_ras_eeprom_init() -> amdgpu_ras_eeprom_reset_table()

Type Parameter Key Value
PARAM_VALUE 0 control 4096-ptr_max
PARAM_VALUE 0 control->i2c_address 0,65536-196608,262144
PARAM_VALUE 0 control->ras_header_offset 0
PARAM_VALUE 0 control->ras_info_offset 20
PARAM_VALUE 0 control->ras_tbl_mutex.dep_map->name 0-255
PARAM_VALUE 0 control->ras_tbl_mutex.first_waiter 0
PARAM_VALUE 0 control->ras_tbl_mutex.magic 4096-ptr_max
PARAM_VALUE 0 control->ras_tbl_mutex.osq.tail.counter 0
PARAM_VALUE 0 control->ras_tbl_mutex.owner.counter 0
PARAM_VALUE 0 control->tbl_hdr.header 1095582802,1111573575
PARAM_VALUE 0 control->tbl_hdr.version 0-196607
BUF_SIZE 0 control 480
DATA_SOURCE 0 control $0
FUZZY_MAX 0 control->tbl_hdr.version 196607
HARD_MAX 0 control->tbl_hdr.version 196607

drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c amdgpu_ras_eeprom_init() -> amdgpu_ras_eeprom_reset_table()

Type Parameter Key Value
PARAM_VALUE 0 control 4096-ptr_max
PARAM_VALUE 0 control->i2c_address 0,65536-196608,262144
PARAM_VALUE 0 control->ras_header_offset 0
PARAM_VALUE 0 control->ras_info_offset 20
PARAM_VALUE 0 control->ras_tbl_mutex.dep_map->name 0-255
PARAM_VALUE 0 control->ras_tbl_mutex.first_waiter 0
PARAM_VALUE 0 control->ras_tbl_mutex.magic 4096-ptr_max
PARAM_VALUE 0 control->ras_tbl_mutex.osq.tail.counter 0
PARAM_VALUE 0 control->ras_tbl_mutex.owner.counter 0
PARAM_VALUE 0 control->tbl_hdr.header 1095582802,1111573575
PARAM_VALUE 0 control->tbl_hdr.tbl_size 0-275
BUF_SIZE 0 control 480
DATA_SOURCE 0 control $0
FUZZY_MAX 0 control->tbl_hdr.tbl_size 275
HARD_MAX 0 control->tbl_hdr.tbl_size 275

drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c amdgpu_ras_eeprom_init() -> amdgpu_ras_eeprom_reset_table()

Type Parameter Key Value
PARAM_VALUE 0 control 4096-ptr_max
PARAM_VALUE 0 control->i2c_address 0,65536-196608,262144
PARAM_VALUE 0 control->ras_header_offset 0
PARAM_VALUE 0 control->ras_info_offset 20
PARAM_VALUE 0 control->ras_tbl_mutex.dep_map->name 0-255
PARAM_VALUE 0 control->ras_tbl_mutex.first_waiter 0
PARAM_VALUE 0 control->ras_tbl_mutex.magic 4096-ptr_max
PARAM_VALUE 0 control->ras_tbl_mutex.osq.tail.counter 0
PARAM_VALUE 0 control->ras_tbl_mutex.owner.counter 0
PARAM_VALUE 0 control->tbl_hdr.header 1095582802,1111573575
PARAM_VALUE 0 control->tbl_hdr.tbl_size 0-19
BUF_SIZE 0 control 480
DATA_SOURCE 0 control $0
FUZZY_MAX 0 control->tbl_hdr.tbl_size 19
HARD_MAX 0 control->tbl_hdr.tbl_size 19

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c amdgpu_ras_debugfs_eeprom_write() -> amdgpu_ras_eeprom_reset_table()

Type Parameter Key Value
PARAM_VALUE 0 control 4096-ptr_max