Defined in 1 files as a prototype:
Defined in 1 files as a function:
Referenced in 2 files:
Smatch caller information:
drivers/video/fbdev/aty/radeon_base.c radeon_pll_errata_after_data_slow() -> _radeon_msleep()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | rinfo | 4096-ptr_max |
| PARAM_VALUE | 0 | rinfo->errata | 4-u32max |
| PARAM_VALUE | 0 | rinfo->panel_info.hAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->panel_info.pwr_delay | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.ref_divider | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.use_bios_dividers | 1 |
| PARAM_VALUE | 0 | rinfo->panel_info.vAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->reinit_func | 74877280292859904 |
| PARAM_VALUE | 0 | rinfo->video_ram | 0,8388608,16777216-520093696 |
| PARAM_VALUE | 1 | ms | 5 |
| BUF_SIZE | 0 | rinfo | (-1),2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| BUF_SIZE | 0 | rinfo | (-1),2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| DATA_SOURCE | 0 | rinfo | $0 |
| BIT_INFO | 0 | rinfo->errata | 0x4,0xffffffff |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HOST_DATA | 0 | rinfo->init_state.lvds_gen_cntl | 0-u32max[c] |
| HOST_DATA | 0 | rinfo->pending_lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_h_total_disp | 0-u32max[c] |
| HOST_DATA | 0 | rinfo->state.crtc_pitch | 0-u32max[c] |
| HOST_DATA | 0 | rinfo->state.crtc_v_total_disp | 0-u32max[c] |
| HOST_DATA | 0 | rinfo->state.fp_crtc_h_total_disp | 0-u32max[c] |
| HOST_DATA | 0 | rinfo->state.fp_crtc_v_total_disp | 0-u32max[c] |
| NO_OVERFLOW_SIMPLE | 0 | rinfo->panel_info.xres | |
| NO_OVERFLOW_SIMPLE | 0 | rinfo->panel_info.yres | |
| UNITS | 0 | rinfo | unit_byte |
| HALF_LOCKED2 | global &console_sem |
drivers/video/fbdev/aty/radeon_base.c radeon_screen_blank() -> _radeon_msleep()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | rinfo | 4096-ptr_max |
| PARAM_VALUE | 0 | rinfo->dp_gui_master_cntl | 268435456,268435968-268436480,268436992 |
| PARAM_VALUE | 0 | rinfo->lock_blank | 0 |
| PARAM_VALUE | 0 | rinfo->lvds_timer.entry.pprev | 0 |
| PARAM_VALUE | 0 | rinfo->lvds_timer.flags | 0-4194302 |
| PARAM_VALUE | 0 | rinfo->lvds_timer.function | 0 |
| PARAM_VALUE | 0 | rinfo->mon1_type | 2 |
| PARAM_VALUE | 0 | rinfo->panel_info.hAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->panel_info.pwr_delay | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.ref_divider | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.use_bios_dividers | 1 |
| PARAM_VALUE | 0 | rinfo->panel_info.vAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->reinit_func | 74877280292859904 |
| PARAM_VALUE | 0 | rinfo->video_ram | 0,8388608,16777216-520093696 |
| PARAM_VALUE | 1 | ms | 0-u16max |
| BUF_SIZE | 0 | rinfo | 2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| BUF_SIZE | 0 | rinfo | 2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| CAPPED_DATA | 0 | &rinfo->lvds_timer | 1 |
| DATA_SOURCE | 0 | rinfo | $0 |
| BIT_INFO | 0 | rinfo->init_state.lvds_gen_cntl | 0x80001,0xfffffffd |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HOST_DATA | 0 | rinfo->fb_local_base | 0,65536-4294901760 |
| HOST_DATA | 0 | rinfo->init_state.lvds_gen_cntl | 0-u32max[c] |
| NO_OVERFLOW_SIMPLE | 0 | rinfo->panel_info.xres | |
| NO_OVERFLOW_SIMPLE | 0 | rinfo->panel_info.yres | |
| UNITS | 0 | rinfo | unit_byte |
| LOCK2 | global &console_sem | ||
| HALF_LOCKED2 | &fsm->lock |
drivers/video/fbdev/aty/radeon_base.c radeon_write_pll_regs() -> _radeon_msleep()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | rinfo | 4096-ptr_max |
| PARAM_VALUE | 0 | rinfo->panel_info.hAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->panel_info.ref_divider | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.use_bios_dividers | 1 |
| PARAM_VALUE | 0 | rinfo->panel_info.vAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->reg_lock.rlock.dep_map->name | 0-255 |
| PARAM_VALUE | 0 | rinfo->reinit_func | 74877280292859904 |
| PARAM_VALUE | 0 | rinfo->video_ram | 0,8388608,16777216-520093696 |
| PARAM_VALUE | 1 | ms | 5 |
| BUF_SIZE | 0 | rinfo | 2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| BUF_SIZE | 0 | rinfo | 2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| DATA_SOURCE | 0 | rinfo | $0 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HOST_DATA | 0 | rinfo->init_state.lvds_gen_cntl | 0-u32max[c] |
| HOST_DATA | 0 | rinfo->pending_lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_h_total_disp | 0-u32max[c] |
| HOST_DATA | 0 | rinfo->state.crtc_pitch | 0-u32max[c] |
| HOST_DATA | 0 | rinfo->state.crtc_v_total_disp | 0-u32max[c] |
| HOST_DATA | 0 | rinfo->state.fp_crtc_h_total_disp | 0-u32max[c] |
| HOST_DATA | 0 | rinfo->state.fp_crtc_v_total_disp | 0-u32max[c] |
| NO_OVERFLOW_SIMPLE | 0 | rinfo->panel_info.xres | |
| NO_OVERFLOW_SIMPLE | 0 | rinfo->panel_info.yres | |
| UNITS | 0 | rinfo | unit_byte |
| HALF_LOCKED2 | global &console_sem |
drivers/video/fbdev/aty/radeon_pm.c radeon_pm_disable_dynamic_mode() -> _radeon_msleep()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | rinfo | 4096-ptr_max |
| PARAM_VALUE | 0 | rinfo->dp_gui_master_cntl | 268435456,268435968-268436480,268436992 |
| PARAM_VALUE | 0 | rinfo->dynclk | (-1)-s32max |
| PARAM_VALUE | 0 | rinfo->family | 0-12,14-255 |
| PARAM_VALUE | 0 | rinfo->fp_bios_start | 0-u16max |
| PARAM_VALUE | 0 | rinfo->has_CRTC2 | s32min-(-1),1-s32max |
| PARAM_VALUE | 0 | rinfo->lvds_timer.entry.pprev | 0 |
| PARAM_VALUE | 0 | rinfo->lvds_timer.flags | 0-4194302 |
| PARAM_VALUE | 0 | rinfo->panel_info.fbk_divider | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.hAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->panel_info.post_divider | 0-255 |
| PARAM_VALUE | 0 | rinfo->panel_info.pwr_delay | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.ref_divider | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.use_bios_dividers | 1 |
| PARAM_VALUE | 0 | rinfo->panel_info.vAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->panel_info.valid | 1 |
| PARAM_VALUE | 0 | rinfo->reinit_func | 74877280292859904 |
| PARAM_VALUE | 0 | rinfo->reversed_DAC | 0-s32max |
| PARAM_VALUE | 0 | rinfo->reversed_TMDS | 1 |
| PARAM_VALUE | 0 | rinfo->video_ram | 0,8388608,16777216-520093696 |
| PARAM_VALUE | 0 | rinfo->vram_ddr | 0-1 |
| PARAM_VALUE | 0 | rinfo->vram_width | 32,64,128,256 |
| PARAM_VALUE | 1 | ms | 16 |
| BUF_SIZE | 0 | rinfo | 2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| BUF_SIZE | 0 | rinfo | 2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| BUF_SIZE | 0 | rinfo->pdev | (-1),16,24,40,56,108-1096,1384,1600,1616,1752,2072,2576,7472,8064 |
| DATA_SOURCE | 0 | rinfo | $0 |
| FUZZY_MAX | 0 | rinfo->family | 3 |
| FUZZY_MAX | 0 | rinfo->has_CRTC2 | 1 |
| STR_LEN | 0 | rinfo->name | (-1),49 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HOST_DATA | 0 | rinfo->fb_local_base | 0,65536-4294901760 |
| HOST_DATA | 0 | rinfo->fp_bios_start | 0-u16max |
| HOST_DATA | 0 | rinfo->init_state.amcgpio_en_reg | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.amcgpio_mask | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.bios_5_scratch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.bus_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.cap0_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.cap1_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.clk_cntl_index | 0,64-u32max |
| HOST_DATA | 0 | rinfo->init_state.clock_cntl_index | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_ext_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_more_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dac2_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dac_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp2_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_hw_debug | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_output_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dot_clock_freq | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dot_clock_freq_2 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dp_datatype | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.feedback_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.feedback_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_horz_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_panel_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_vert_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.gen_int_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.grph2_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.grph_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.htotal_cntl2 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.i2c_cntl_1 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.lvds_pll_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.mpp_gp_config | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.mpp_tb_config | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ov0_scale_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_clr | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_wid_left_right | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_wid_top_bottom | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.p2pll_div_0 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.p2pll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.palette_valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.post_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.post_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.ppll_div_3 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ppll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.rbbm_soft_reset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.subpic_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.surface_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.tmds_crc | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.tmds_transmitter_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.vclk_ecp_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.viph_control | 0-u32max |
| HOST_DATA | 0 | rinfo->panel_info->clock | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->fbk_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hAct_high | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hOver_plus | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hSync_width | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hblank | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->interlaced | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->post_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->pwr_delay | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->ref_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->use_bios_dividers | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vAct_high | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vOver_plus | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vSync_width | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vblank | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->xres | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->yres | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info.clock | 0-u16max |
| HOST_DATA | 0 | rinfo->panel_info.fbk_divider | 0-u16max |
| HOST_DATA | 0 | rinfo->panel_info.hOver_plus | 0-s16max[c] |
| HOST_DATA | 0 | rinfo->panel_info.hSync_width | 0-2040 |
| HOST_DATA | 0 | rinfo->panel_info.hblank | (-524280)-(-8),0-524280[c] |
| HOST_DATA | 0 | rinfo->panel_info.post_divider | 0-255 |
| HOST_DATA | 0 | rinfo->panel_info.vOver_plus | (-65535)-255 |
| HOST_DATA | 0 | rinfo->panel_info.vSync_width | 0[c] |
| HOST_DATA | 0 | rinfo->panel_info.vblank | (-65535)-u16max |
| HOST_DATA | 0 | rinfo->panel_info.xres | 9-4096[c] |
| HOST_DATA | 0 | rinfo->panel_info.yres | 0-u16max[c] |
| HOST_DATA | 0 | rinfo->pdev->current_state | 0-3[c] |
| HOST_DATA | 0 | rinfo->pending_lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->pll.ppll_max | s32min-s32max |
| HOST_DATA | 0 | rinfo->pll.ppll_min | s32min-s32max |
| HOST_DATA | 0 | rinfo->pll.ref_clk | 0-u16max |
| HOST_DATA | 0 | rinfo->pll.ref_div | 0-u16max |
| HOST_DATA | 0 | rinfo->state.amcgpio_en_reg | 0-u32max |
| HOST_DATA | 0 | rinfo->state.amcgpio_mask | 0-u32max |
| HOST_DATA | 0 | rinfo->state.bios_5_scratch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.bus_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.cap0_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.cap1_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.clk_cntl_index | 0,64-u32max |
| HOST_DATA | 0 | rinfo->state.clock_cntl_index | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_ext_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_more_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dac2_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dac_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp2_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_hw_debug | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_output_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dot_clock_freq | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dot_clock_freq_2 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dp_datatype | 0-u32max |
| HOST_DATA | 0 | rinfo->state.feedback_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.feedback_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.fp2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_horz_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_panel_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_vert_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.gen_int_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.grph2_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.grph_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.htotal_cntl2 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.i2c_cntl_1 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.lvds_pll_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.mpp_gp_config | 0-u32max |
| HOST_DATA | 0 | rinfo->state.mpp_tb_config | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ov0_scale_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_clr | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_wid_left_right | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_wid_top_bottom | 0-u32max |
| HOST_DATA | 0 | rinfo->state.p2pll_div_0 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.p2pll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->state.palette_valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.post_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.post_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.ppll_div_3 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ppll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->state.rbbm_soft_reset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.subpic_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.surface_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.tmds_crc | 0-u32max |
| HOST_DATA | 0 | rinfo->state.tmds_transmitter_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.vclk_ecp_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.viph_control | 0-u32max |
| UNITS | 0 | rinfo | unit_byte |
| HALF_LOCKED2 | global &console_sem |
drivers/video/fbdev/aty/radeon_pm.c radeon_pm_disable_dynamic_mode() -> _radeon_msleep()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | rinfo | 4096-ptr_max |
| PARAM_VALUE | 0 | rinfo->dp_gui_master_cntl | 268435456,268435968-268436480,268436992 |
| PARAM_VALUE | 0 | rinfo->dynclk | (-1)-s32max |
| PARAM_VALUE | 0 | rinfo->family | 11-12 |
| PARAM_VALUE | 0 | rinfo->fp_bios_start | 0-u16max |
| PARAM_VALUE | 0 | rinfo->has_CRTC2 | s32min-(-1),1-s32max |
| PARAM_VALUE | 0 | rinfo->lvds_timer.entry.pprev | 0 |
| PARAM_VALUE | 0 | rinfo->lvds_timer.flags | 0-4194302 |
| PARAM_VALUE | 0 | rinfo->panel_info.fbk_divider | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.hAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->panel_info.post_divider | 0-255 |
| PARAM_VALUE | 0 | rinfo->panel_info.pwr_delay | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.ref_divider | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.use_bios_dividers | 1 |
| PARAM_VALUE | 0 | rinfo->panel_info.vAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->panel_info.valid | 1 |
| PARAM_VALUE | 0 | rinfo->reinit_func | 74877280292859904 |
| PARAM_VALUE | 0 | rinfo->reversed_DAC | 0-s32max |
| PARAM_VALUE | 0 | rinfo->reversed_TMDS | 1 |
| PARAM_VALUE | 0 | rinfo->video_ram | 0,8388608,16777216-520093696 |
| PARAM_VALUE | 0 | rinfo->vram_ddr | 0-1 |
| PARAM_VALUE | 0 | rinfo->vram_width | 32,64,128,256 |
| PARAM_VALUE | 1 | ms | 16 |
| BUF_SIZE | 0 | rinfo | 2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| BUF_SIZE | 0 | rinfo | 2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| BUF_SIZE | 0 | rinfo->pdev | (-1),16,24,40,56,108-1096,1384,1600,1616,1752,2072,2576,7472,8064 |
| DATA_SOURCE | 0 | rinfo | $0 |
| FUZZY_MAX | 0 | rinfo->has_CRTC2 | 1 |
| STR_LEN | 0 | rinfo->name | (-1),49 |
| BIT_INFO | 0 | rinfo->family | 0x8,0xf |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HOST_DATA | 0 | rinfo->fb_local_base | 0,65536-4294901760 |
| HOST_DATA | 0 | rinfo->fp_bios_start | 0-u16max |
| HOST_DATA | 0 | rinfo->init_state.amcgpio_en_reg | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.amcgpio_mask | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.bios_5_scratch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.bus_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.cap0_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.cap1_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.clk_cntl_index | 0,64-u32max |
| HOST_DATA | 0 | rinfo->init_state.clock_cntl_index | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_ext_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_more_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dac2_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dac_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp2_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_hw_debug | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_output_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dot_clock_freq | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dot_clock_freq_2 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dp_datatype | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.feedback_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.feedback_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_horz_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_panel_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_vert_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.gen_int_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.grph2_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.grph_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.htotal_cntl2 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.i2c_cntl_1 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.lvds_pll_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.mpp_gp_config | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.mpp_tb_config | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ov0_scale_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_clr | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_wid_left_right | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_wid_top_bottom | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.p2pll_div_0 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.p2pll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.palette_valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.post_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.post_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.ppll_div_3 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ppll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.rbbm_soft_reset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.subpic_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.surface_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.tmds_crc | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.tmds_transmitter_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.vclk_ecp_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.viph_control | 0-u32max |
| HOST_DATA | 0 | rinfo->panel_info->clock | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->fbk_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hAct_high | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hOver_plus | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hSync_width | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hblank | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->interlaced | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->post_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->pwr_delay | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->ref_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->use_bios_dividers | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vAct_high | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vOver_plus | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vSync_width | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vblank | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->xres | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->yres | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info.clock | 0-u16max |
| HOST_DATA | 0 | rinfo->panel_info.fbk_divider | 0-u16max |
| HOST_DATA | 0 | rinfo->panel_info.hOver_plus | 0-s16max[c] |
| HOST_DATA | 0 | rinfo->panel_info.hSync_width | 0-2040 |
| HOST_DATA | 0 | rinfo->panel_info.hblank | (-524280)-(-8),0-524280[c] |
| HOST_DATA | 0 | rinfo->panel_info.post_divider | 0-255 |
| HOST_DATA | 0 | rinfo->panel_info.vOver_plus | (-65535)-255 |
| HOST_DATA | 0 | rinfo->panel_info.vSync_width | 0[c] |
| HOST_DATA | 0 | rinfo->panel_info.vblank | (-65535)-u16max |
| HOST_DATA | 0 | rinfo->panel_info.xres | 9-4096[c] |
| HOST_DATA | 0 | rinfo->panel_info.yres | 0-u16max[c] |
| HOST_DATA | 0 | rinfo->pdev->current_state | 0-3[c] |
| HOST_DATA | 0 | rinfo->pending_lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->pll.ppll_max | s32min-s32max |
| HOST_DATA | 0 | rinfo->pll.ppll_min | s32min-s32max |
| HOST_DATA | 0 | rinfo->pll.ref_clk | 0-u16max |
| HOST_DATA | 0 | rinfo->pll.ref_div | 0-u16max |
| HOST_DATA | 0 | rinfo->state.amcgpio_en_reg | 0-u32max |
| HOST_DATA | 0 | rinfo->state.amcgpio_mask | 0-u32max |
| HOST_DATA | 0 | rinfo->state.bios_5_scratch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.bus_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.cap0_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.cap1_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.clk_cntl_index | 0,64-u32max |
| HOST_DATA | 0 | rinfo->state.clock_cntl_index | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_ext_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_more_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dac2_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dac_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp2_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_hw_debug | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_output_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dot_clock_freq | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dot_clock_freq_2 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dp_datatype | 0-u32max |
| HOST_DATA | 0 | rinfo->state.feedback_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.feedback_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.fp2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_horz_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_panel_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_vert_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.gen_int_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.grph2_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.grph_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.htotal_cntl2 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.i2c_cntl_1 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.lvds_pll_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.mpp_gp_config | 0-u32max |
| HOST_DATA | 0 | rinfo->state.mpp_tb_config | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ov0_scale_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_clr | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_wid_left_right | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_wid_top_bottom | 0-u32max |
| HOST_DATA | 0 | rinfo->state.p2pll_div_0 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.p2pll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->state.palette_valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.post_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.post_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.ppll_div_3 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ppll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->state.rbbm_soft_reset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.subpic_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.surface_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.tmds_crc | 0-u32max |
| HOST_DATA | 0 | rinfo->state.tmds_transmitter_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.vclk_ecp_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.viph_control | 0-u32max |
| UNITS | 0 | rinfo | unit_byte |
| HALF_LOCKED2 | global &console_sem |
drivers/video/fbdev/aty/radeon_pm.c radeon_pm_disable_dynamic_mode() -> _radeon_msleep()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | rinfo | 4096-ptr_max |
| PARAM_VALUE | 0 | rinfo->dp_gui_master_cntl | 268435456,268435968-268436480,268436992 |
| PARAM_VALUE | 0 | rinfo->dynclk | (-1)-s32max |
| PARAM_VALUE | 0 | rinfo->family | 0-12,14-255 |
| PARAM_VALUE | 0 | rinfo->fp_bios_start | 0-u16max |
| PARAM_VALUE | 0 | rinfo->has_CRTC2 | s32min-(-1),1-s32max |
| PARAM_VALUE | 0 | rinfo->lvds_timer.entry.pprev | 0 |
| PARAM_VALUE | 0 | rinfo->lvds_timer.flags | 0-4194302 |
| PARAM_VALUE | 0 | rinfo->panel_info.fbk_divider | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.hAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->panel_info.post_divider | 0-255 |
| PARAM_VALUE | 0 | rinfo->panel_info.pwr_delay | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.ref_divider | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.use_bios_dividers | 1 |
| PARAM_VALUE | 0 | rinfo->panel_info.vAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->panel_info.valid | 1 |
| PARAM_VALUE | 0 | rinfo->reinit_func | 74877280292859904 |
| PARAM_VALUE | 0 | rinfo->reversed_DAC | 0-s32max |
| PARAM_VALUE | 0 | rinfo->reversed_TMDS | 1 |
| PARAM_VALUE | 0 | rinfo->video_ram | 0,8388608,16777216-520093696 |
| PARAM_VALUE | 0 | rinfo->vram_ddr | 0-1 |
| PARAM_VALUE | 0 | rinfo->vram_width | 32,64,128,256 |
| PARAM_VALUE | 1 | ms | 15 |
| BUF_SIZE | 0 | rinfo | 2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| BUF_SIZE | 0 | rinfo | 2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| BUF_SIZE | 0 | rinfo->pdev | (-1),16,24,40,56,108-1096,1384,1600,1616,1752,2072,2576,7472,8064 |
| DATA_SOURCE | 0 | rinfo | $0 |
| FUZZY_MAX | 0 | rinfo->family | 3 |
| FUZZY_MAX | 0 | rinfo->has_CRTC2 | 1 |
| STR_LEN | 0 | rinfo->name | (-1),49 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HOST_DATA | 0 | rinfo->fb_local_base | 0,65536-4294901760 |
| HOST_DATA | 0 | rinfo->fp_bios_start | 0-u16max |
| HOST_DATA | 0 | rinfo->init_state.amcgpio_en_reg | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.amcgpio_mask | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.bios_5_scratch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.bus_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.cap0_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.cap1_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.clk_cntl_index | 0,64-u32max |
| HOST_DATA | 0 | rinfo->init_state.clock_cntl_index | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_ext_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_more_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dac2_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dac_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp2_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_hw_debug | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_output_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dot_clock_freq | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dot_clock_freq_2 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dp_datatype | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.feedback_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.feedback_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_horz_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_panel_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_vert_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.gen_int_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.grph2_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.grph_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.htotal_cntl2 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.i2c_cntl_1 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.lvds_pll_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.mpp_gp_config | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.mpp_tb_config | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ov0_scale_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_clr | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_wid_left_right | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_wid_top_bottom | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.p2pll_div_0 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.p2pll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.palette_valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.post_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.post_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.ppll_div_3 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ppll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.rbbm_soft_reset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.subpic_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.surface_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.tmds_crc | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.tmds_transmitter_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.vclk_ecp_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.viph_control | 0-u32max |
| HOST_DATA | 0 | rinfo->panel_info->clock | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->fbk_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hAct_high | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hOver_plus | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hSync_width | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hblank | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->interlaced | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->post_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->pwr_delay | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->ref_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->use_bios_dividers | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vAct_high | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vOver_plus | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vSync_width | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vblank | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->xres | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->yres | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info.clock | 0-u16max |
| HOST_DATA | 0 | rinfo->panel_info.fbk_divider | 0-u16max |
| HOST_DATA | 0 | rinfo->panel_info.hOver_plus | 0-s16max[c] |
| HOST_DATA | 0 | rinfo->panel_info.hSync_width | 0-2040 |
| HOST_DATA | 0 | rinfo->panel_info.hblank | (-524280)-(-8),0-524280[c] |
| HOST_DATA | 0 | rinfo->panel_info.post_divider | 0-255 |
| HOST_DATA | 0 | rinfo->panel_info.vOver_plus | (-65535)-255 |
| HOST_DATA | 0 | rinfo->panel_info.vSync_width | 0[c] |
| HOST_DATA | 0 | rinfo->panel_info.vblank | (-65535)-u16max |
| HOST_DATA | 0 | rinfo->panel_info.xres | 9-4096[c] |
| HOST_DATA | 0 | rinfo->panel_info.yres | 0-u16max[c] |
| HOST_DATA | 0 | rinfo->pdev->current_state | 0-3[c] |
| HOST_DATA | 0 | rinfo->pending_lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->pll.ppll_max | s32min-s32max |
| HOST_DATA | 0 | rinfo->pll.ppll_min | s32min-s32max |
| HOST_DATA | 0 | rinfo->pll.ref_clk | 0-u16max |
| HOST_DATA | 0 | rinfo->pll.ref_div | 0-u16max |
| HOST_DATA | 0 | rinfo->state.amcgpio_en_reg | 0-u32max |
| HOST_DATA | 0 | rinfo->state.amcgpio_mask | 0-u32max |
| HOST_DATA | 0 | rinfo->state.bios_5_scratch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.bus_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.cap0_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.cap1_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.clk_cntl_index | 0,64-u32max |
| HOST_DATA | 0 | rinfo->state.clock_cntl_index | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_ext_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_more_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dac2_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dac_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp2_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_hw_debug | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_output_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dot_clock_freq | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dot_clock_freq_2 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dp_datatype | 0-u32max |
| HOST_DATA | 0 | rinfo->state.feedback_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.feedback_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.fp2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_horz_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_panel_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_vert_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.gen_int_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.grph2_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.grph_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.htotal_cntl2 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.i2c_cntl_1 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.lvds_pll_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.mpp_gp_config | 0-u32max |
| HOST_DATA | 0 | rinfo->state.mpp_tb_config | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ov0_scale_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_clr | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_wid_left_right | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_wid_top_bottom | 0-u32max |
| HOST_DATA | 0 | rinfo->state.p2pll_div_0 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.p2pll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->state.palette_valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.post_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.post_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.ppll_div_3 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ppll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->state.rbbm_soft_reset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.subpic_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.surface_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.tmds_crc | 0-u32max |
| HOST_DATA | 0 | rinfo->state.tmds_transmitter_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.vclk_ecp_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.viph_control | 0-u32max |
| UNITS | 0 | rinfo | unit_byte |
| HALF_LOCKED2 | global &console_sem |
drivers/video/fbdev/aty/radeon_pm.c radeon_pm_disable_dynamic_mode() -> _radeon_msleep()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | rinfo | 4096-ptr_max |
| PARAM_VALUE | 0 | rinfo->dp_gui_master_cntl | 268435456,268435968-268436480,268436992 |
| PARAM_VALUE | 0 | rinfo->dynclk | (-1)-s32max |
| PARAM_VALUE | 0 | rinfo->family | 0-12,14-255 |
| PARAM_VALUE | 0 | rinfo->fp_bios_start | 0-u16max |
| PARAM_VALUE | 0 | rinfo->has_CRTC2 | s32min-(-1),1-s32max |
| PARAM_VALUE | 0 | rinfo->is_IGP | s32min-(-1),1-s32max |
| PARAM_VALUE | 0 | rinfo->lvds_timer.entry.pprev | 0 |
| PARAM_VALUE | 0 | rinfo->lvds_timer.flags | 0-4194302 |
| PARAM_VALUE | 0 | rinfo->panel_info.fbk_divider | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.hAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->panel_info.post_divider | 0-255 |
| PARAM_VALUE | 0 | rinfo->panel_info.pwr_delay | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.ref_divider | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.use_bios_dividers | 1 |
| PARAM_VALUE | 0 | rinfo->panel_info.vAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->panel_info.valid | 1 |
| PARAM_VALUE | 0 | rinfo->reinit_func | 74877280292859904 |
| PARAM_VALUE | 0 | rinfo->reversed_DAC | 0-s32max |
| PARAM_VALUE | 0 | rinfo->reversed_TMDS | 1 |
| PARAM_VALUE | 0 | rinfo->video_ram | 0,8388608,16777216-520093696 |
| PARAM_VALUE | 0 | rinfo->vram_ddr | 0-1 |
| PARAM_VALUE | 0 | rinfo->vram_width | 32,64,128,256 |
| PARAM_VALUE | 1 | ms | 16 |
| BUF_SIZE | 0 | rinfo | 2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| BUF_SIZE | 0 | rinfo | 2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| BUF_SIZE | 0 | rinfo->pdev | (-1),16,24,40,56,108-1096,1384,1600,1616,1752,2072,2576,7472,8064 |
| DATA_SOURCE | 0 | rinfo | $0 |
| FUZZY_MAX | 0 | rinfo->family | 3 |
| FUZZY_MAX | 0 | rinfo->has_CRTC2 | 1 |
| FUZZY_MAX | 0 | rinfo->is_IGP | 1 |
| STR_LEN | 0 | rinfo->name | (-1),49 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HOST_DATA | 0 | rinfo->fb_local_base | 0,65536-4294901760 |
| HOST_DATA | 0 | rinfo->fp_bios_start | 0-u16max |
| HOST_DATA | 0 | rinfo->init_state.amcgpio_en_reg | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.amcgpio_mask | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.bios_5_scratch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.bus_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.cap0_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.cap1_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.clk_cntl_index | 0,64-u32max |
| HOST_DATA | 0 | rinfo->init_state.clock_cntl_index | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_ext_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_more_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dac2_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dac_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp2_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_hw_debug | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_output_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dot_clock_freq | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dot_clock_freq_2 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dp_datatype | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.feedback_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.feedback_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_horz_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_panel_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_vert_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.gen_int_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.grph2_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.grph_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.htotal_cntl2 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.i2c_cntl_1 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.lvds_pll_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.mpp_gp_config | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.mpp_tb_config | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ov0_scale_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_clr | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_wid_left_right | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_wid_top_bottom | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.p2pll_div_0 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.p2pll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.palette_valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.post_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.post_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.ppll_div_3 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ppll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.rbbm_soft_reset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.subpic_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.surface_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.tmds_crc | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.tmds_transmitter_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.vclk_ecp_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.viph_control | 0-u32max |
| HOST_DATA | 0 | rinfo->panel_info->clock | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->fbk_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hAct_high | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hOver_plus | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hSync_width | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hblank | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->interlaced | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->post_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->pwr_delay | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->ref_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->use_bios_dividers | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vAct_high | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vOver_plus | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vSync_width | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vblank | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->xres | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->yres | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info.clock | 0-u16max |
| HOST_DATA | 0 | rinfo->panel_info.fbk_divider | 0-u16max |
| HOST_DATA | 0 | rinfo->panel_info.hOver_plus | 0-s16max[c] |
| HOST_DATA | 0 | rinfo->panel_info.hSync_width | 0-2040 |
| HOST_DATA | 0 | rinfo->panel_info.hblank | (-524280)-(-8),0-524280[c] |
| HOST_DATA | 0 | rinfo->panel_info.post_divider | 0-255 |
| HOST_DATA | 0 | rinfo->panel_info.vOver_plus | (-65535)-255 |
| HOST_DATA | 0 | rinfo->panel_info.vSync_width | 0[c] |
| HOST_DATA | 0 | rinfo->panel_info.vblank | (-65535)-u16max |
| HOST_DATA | 0 | rinfo->panel_info.xres | 9-4096[c] |
| HOST_DATA | 0 | rinfo->panel_info.yres | 0-u16max[c] |
| HOST_DATA | 0 | rinfo->pdev->current_state | 0-3[c] |
| HOST_DATA | 0 | rinfo->pending_lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->pll.ppll_max | s32min-s32max |
| HOST_DATA | 0 | rinfo->pll.ppll_min | s32min-s32max |
| HOST_DATA | 0 | rinfo->pll.ref_clk | 0-u16max |
| HOST_DATA | 0 | rinfo->pll.ref_div | 0-u16max |
| HOST_DATA | 0 | rinfo->state.amcgpio_en_reg | 0-u32max |
| HOST_DATA | 0 | rinfo->state.amcgpio_mask | 0-u32max |
| HOST_DATA | 0 | rinfo->state.bios_5_scratch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.bus_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.cap0_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.cap1_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.clk_cntl_index | 0,64-u32max |
| HOST_DATA | 0 | rinfo->state.clock_cntl_index | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_ext_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_more_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dac2_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dac_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp2_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_hw_debug | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_output_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dot_clock_freq | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dot_clock_freq_2 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dp_datatype | 0-u32max |
| HOST_DATA | 0 | rinfo->state.feedback_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.feedback_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.fp2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_horz_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_panel_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_vert_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.gen_int_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.grph2_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.grph_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.htotal_cntl2 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.i2c_cntl_1 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.lvds_pll_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.mpp_gp_config | 0-u32max |
| HOST_DATA | 0 | rinfo->state.mpp_tb_config | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ov0_scale_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_clr | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_wid_left_right | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_wid_top_bottom | 0-u32max |
| HOST_DATA | 0 | rinfo->state.p2pll_div_0 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.p2pll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->state.palette_valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.post_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.post_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.ppll_div_3 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ppll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->state.rbbm_soft_reset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.subpic_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.surface_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.tmds_crc | 0-u32max |
| HOST_DATA | 0 | rinfo->state.tmds_transmitter_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.vclk_ecp_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.viph_control | 0-u32max |
| UNITS | 0 | rinfo | unit_byte |
| HALF_LOCKED2 | global &console_sem |
drivers/video/fbdev/aty/radeon_pm.c radeon_pm_disable_dynamic_mode() -> _radeon_msleep()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | rinfo | 4096-ptr_max |
| PARAM_VALUE | 0 | rinfo->dp_gui_master_cntl | 268435456,268435968-268436480,268436992 |
| PARAM_VALUE | 0 | rinfo->dynclk | (-1)-s32max |
| PARAM_VALUE | 0 | rinfo->family | 0-12,14-255 |
| PARAM_VALUE | 0 | rinfo->fp_bios_start | 0-u16max |
| PARAM_VALUE | 0 | rinfo->has_CRTC2 | s32min-(-1),1-s32max |
| PARAM_VALUE | 0 | rinfo->is_IGP | 0 |
| PARAM_VALUE | 0 | rinfo->is_mobility | s32min-(-1),1-s32max |
| PARAM_VALUE | 0 | rinfo->lvds_timer.entry.pprev | 0 |
| PARAM_VALUE | 0 | rinfo->lvds_timer.flags | 0-4194302 |
| PARAM_VALUE | 0 | rinfo->panel_info.fbk_divider | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.hAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->panel_info.post_divider | 0-255 |
| PARAM_VALUE | 0 | rinfo->panel_info.pwr_delay | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.ref_divider | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.use_bios_dividers | 1 |
| PARAM_VALUE | 0 | rinfo->panel_info.vAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->panel_info.valid | 1 |
| PARAM_VALUE | 0 | rinfo->reinit_func | 74877280292859904 |
| PARAM_VALUE | 0 | rinfo->reversed_DAC | 0-s32max |
| PARAM_VALUE | 0 | rinfo->reversed_TMDS | 1 |
| PARAM_VALUE | 0 | rinfo->video_ram | 0,8388608,16777216-520093696 |
| PARAM_VALUE | 0 | rinfo->vram_ddr | 0-1 |
| PARAM_VALUE | 0 | rinfo->vram_width | 32,64,128,256 |
| PARAM_VALUE | 1 | ms | 16 |
| BUF_SIZE | 0 | rinfo | 2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| BUF_SIZE | 0 | rinfo | 2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| BUF_SIZE | 0 | rinfo->pdev | (-1),16,24,40,56,108-1096,1384,1600,1616,1752,2072,2576,7472,8064 |
| DATA_SOURCE | 0 | rinfo | $0 |
| FUZZY_MAX | 0 | rinfo->family | 3 |
| FUZZY_MAX | 0 | rinfo->has_CRTC2 | 1 |
| FUZZY_MAX | 0 | rinfo->is_mobility | 1 |
| STR_LEN | 0 | rinfo->name | (-1),49 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HOST_DATA | 0 | rinfo->fb_local_base | 0,65536-4294901760 |
| HOST_DATA | 0 | rinfo->fp_bios_start | 0-u16max |
| HOST_DATA | 0 | rinfo->init_state.amcgpio_en_reg | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.amcgpio_mask | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.bios_5_scratch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.bus_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.cap0_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.cap1_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.clk_cntl_index | 0,64-u32max |
| HOST_DATA | 0 | rinfo->init_state.clock_cntl_index | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_ext_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_more_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dac2_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dac_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp2_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_hw_debug | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_output_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dot_clock_freq | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dot_clock_freq_2 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dp_datatype | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.feedback_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.feedback_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_horz_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_panel_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_vert_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.gen_int_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.grph2_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.grph_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.htotal_cntl2 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.i2c_cntl_1 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.lvds_pll_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.mpp_gp_config | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.mpp_tb_config | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ov0_scale_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_clr | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_wid_left_right | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_wid_top_bottom | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.p2pll_div_0 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.p2pll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.palette_valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.post_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.post_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.ppll_div_3 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ppll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.rbbm_soft_reset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.subpic_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.surface_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.tmds_crc | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.tmds_transmitter_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.vclk_ecp_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.viph_control | 0-u32max |
| HOST_DATA | 0 | rinfo->panel_info->clock | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->fbk_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hAct_high | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hOver_plus | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hSync_width | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hblank | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->interlaced | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->post_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->pwr_delay | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->ref_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->use_bios_dividers | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vAct_high | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vOver_plus | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vSync_width | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vblank | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->xres | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->yres | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info.clock | 0-u16max |
| HOST_DATA | 0 | rinfo->panel_info.fbk_divider | 0-u16max |
| HOST_DATA | 0 | rinfo->panel_info.hOver_plus | 0-s16max[c] |
| HOST_DATA | 0 | rinfo->panel_info.hSync_width | 0-2040 |
| HOST_DATA | 0 | rinfo->panel_info.hblank | (-524280)-(-8),0-524280[c] |
| HOST_DATA | 0 | rinfo->panel_info.post_divider | 0-255 |
| HOST_DATA | 0 | rinfo->panel_info.vOver_plus | (-65535)-255 |
| HOST_DATA | 0 | rinfo->panel_info.vSync_width | 0[c] |
| HOST_DATA | 0 | rinfo->panel_info.vblank | (-65535)-u16max |
| HOST_DATA | 0 | rinfo->panel_info.xres | 9-4096[c] |
| HOST_DATA | 0 | rinfo->panel_info.yres | 0-u16max[c] |
| HOST_DATA | 0 | rinfo->pdev->current_state | 0-3[c] |
| HOST_DATA | 0 | rinfo->pending_lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->pll.ppll_max | s32min-s32max |
| HOST_DATA | 0 | rinfo->pll.ppll_min | s32min-s32max |
| HOST_DATA | 0 | rinfo->pll.ref_clk | 0-u16max |
| HOST_DATA | 0 | rinfo->pll.ref_div | 0-u16max |
| HOST_DATA | 0 | rinfo->state.amcgpio_en_reg | 0-u32max |
| HOST_DATA | 0 | rinfo->state.amcgpio_mask | 0-u32max |
| HOST_DATA | 0 | rinfo->state.bios_5_scratch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.bus_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.cap0_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.cap1_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.clk_cntl_index | 0,64-u32max |
| HOST_DATA | 0 | rinfo->state.clock_cntl_index | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_ext_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_more_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dac2_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dac_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp2_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_hw_debug | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_output_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dot_clock_freq | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dot_clock_freq_2 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dp_datatype | 0-u32max |
| HOST_DATA | 0 | rinfo->state.feedback_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.feedback_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.fp2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_horz_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_panel_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_vert_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.gen_int_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.grph2_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.grph_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.htotal_cntl2 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.i2c_cntl_1 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.lvds_pll_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.mpp_gp_config | 0-u32max |
| HOST_DATA | 0 | rinfo->state.mpp_tb_config | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ov0_scale_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_clr | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_wid_left_right | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_wid_top_bottom | 0-u32max |
| HOST_DATA | 0 | rinfo->state.p2pll_div_0 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.p2pll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->state.palette_valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.post_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.post_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.ppll_div_3 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ppll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->state.rbbm_soft_reset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.subpic_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.surface_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.tmds_crc | 0-u32max |
| HOST_DATA | 0 | rinfo->state.tmds_transmitter_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.vclk_ecp_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.viph_control | 0-u32max |
| UNITS | 0 | rinfo | unit_byte |
| HALF_LOCKED2 | global &console_sem |
drivers/video/fbdev/aty/radeon_pm.c radeon_pm_disable_dynamic_mode() -> _radeon_msleep()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | rinfo | 4096-ptr_max |
| PARAM_VALUE | 0 | rinfo->dp_gui_master_cntl | 268435456,268435968-268436480,268436992 |
| PARAM_VALUE | 0 | rinfo->dynclk | (-1)-s32max |
| PARAM_VALUE | 0 | rinfo->family | 0-12,14-255 |
| PARAM_VALUE | 0 | rinfo->fp_bios_start | 0-u16max |
| PARAM_VALUE | 0 | rinfo->has_CRTC2 | s32min-(-1),1-s32max |
| PARAM_VALUE | 0 | rinfo->is_IGP | 0 |
| PARAM_VALUE | 0 | rinfo->is_mobility | s32min-(-1),1-s32max |
| PARAM_VALUE | 0 | rinfo->lvds_timer.entry.pprev | 0 |
| PARAM_VALUE | 0 | rinfo->lvds_timer.flags | 0-4194302 |
| PARAM_VALUE | 0 | rinfo->panel_info.fbk_divider | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.hAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->panel_info.post_divider | 0-255 |
| PARAM_VALUE | 0 | rinfo->panel_info.pwr_delay | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.ref_divider | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.use_bios_dividers | 1 |
| PARAM_VALUE | 0 | rinfo->panel_info.vAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->panel_info.valid | 1 |
| PARAM_VALUE | 0 | rinfo->reinit_func | 74877280292859904 |
| PARAM_VALUE | 0 | rinfo->reversed_DAC | 0-s32max |
| PARAM_VALUE | 0 | rinfo->reversed_TMDS | 1 |
| PARAM_VALUE | 0 | rinfo->video_ram | 0,8388608,16777216-520093696 |
| PARAM_VALUE | 0 | rinfo->vram_ddr | 0-1 |
| PARAM_VALUE | 0 | rinfo->vram_width | 32,64,128,256 |
| PARAM_VALUE | 1 | ms | 15 |
| BUF_SIZE | 0 | rinfo | 2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| BUF_SIZE | 0 | rinfo | 2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| BUF_SIZE | 0 | rinfo->pdev | (-1),16,24,40,56,108-1096,1384,1600,1616,1752,2072,2576,7472,8064 |
| DATA_SOURCE | 0 | rinfo | $0 |
| FUZZY_MAX | 0 | rinfo->family | 3 |
| FUZZY_MAX | 0 | rinfo->has_CRTC2 | 1 |
| FUZZY_MAX | 0 | rinfo->is_mobility | 1 |
| STR_LEN | 0 | rinfo->name | (-1),49 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HOST_DATA | 0 | rinfo->fb_local_base | 0,65536-4294901760 |
| HOST_DATA | 0 | rinfo->fp_bios_start | 0-u16max |
| HOST_DATA | 0 | rinfo->init_state.amcgpio_en_reg | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.amcgpio_mask | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.bios_5_scratch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.bus_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.cap0_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.cap1_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.clk_cntl_index | 0,64-u32max |
| HOST_DATA | 0 | rinfo->init_state.clock_cntl_index | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_ext_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_more_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dac2_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dac_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp2_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_hw_debug | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_output_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dot_clock_freq | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dot_clock_freq_2 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dp_datatype | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.feedback_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.feedback_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_horz_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_panel_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_vert_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.gen_int_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.grph2_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.grph_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.htotal_cntl2 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.i2c_cntl_1 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.lvds_pll_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.mpp_gp_config | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.mpp_tb_config | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ov0_scale_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_clr | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_wid_left_right | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_wid_top_bottom | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.p2pll_div_0 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.p2pll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.palette_valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.post_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.post_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.ppll_div_3 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ppll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.rbbm_soft_reset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.subpic_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.surface_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.tmds_crc | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.tmds_transmitter_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.vclk_ecp_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.viph_control | 0-u32max |
| HOST_DATA | 0 | rinfo->panel_info->clock | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->fbk_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hAct_high | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hOver_plus | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hSync_width | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hblank | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->interlaced | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->post_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->pwr_delay | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->ref_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->use_bios_dividers | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vAct_high | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vOver_plus | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vSync_width | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vblank | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->xres | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->yres | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info.clock | 0-u16max |
| HOST_DATA | 0 | rinfo->panel_info.fbk_divider | 0-u16max |
| HOST_DATA | 0 | rinfo->panel_info.hOver_plus | 0-s16max[c] |
| HOST_DATA | 0 | rinfo->panel_info.hSync_width | 0-2040 |
| HOST_DATA | 0 | rinfo->panel_info.hblank | (-524280)-(-8),0-524280[c] |
| HOST_DATA | 0 | rinfo->panel_info.post_divider | 0-255 |
| HOST_DATA | 0 | rinfo->panel_info.vOver_plus | (-65535)-255 |
| HOST_DATA | 0 | rinfo->panel_info.vSync_width | 0[c] |
| HOST_DATA | 0 | rinfo->panel_info.vblank | (-65535)-u16max |
| HOST_DATA | 0 | rinfo->panel_info.xres | 9-4096[c] |
| HOST_DATA | 0 | rinfo->panel_info.yres | 0-u16max[c] |
| HOST_DATA | 0 | rinfo->pdev->current_state | 0-3[c] |
| HOST_DATA | 0 | rinfo->pending_lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->pll.ppll_max | s32min-s32max |
| HOST_DATA | 0 | rinfo->pll.ppll_min | s32min-s32max |
| HOST_DATA | 0 | rinfo->pll.ref_clk | 0-u16max |
| HOST_DATA | 0 | rinfo->pll.ref_div | 0-u16max |
| HOST_DATA | 0 | rinfo->state.amcgpio_en_reg | 0-u32max |
| HOST_DATA | 0 | rinfo->state.amcgpio_mask | 0-u32max |
| HOST_DATA | 0 | rinfo->state.bios_5_scratch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.bus_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.cap0_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.cap1_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.clk_cntl_index | 0,64-u32max |
| HOST_DATA | 0 | rinfo->state.clock_cntl_index | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_ext_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_more_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dac2_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dac_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp2_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_hw_debug | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_output_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dot_clock_freq | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dot_clock_freq_2 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dp_datatype | 0-u32max |
| HOST_DATA | 0 | rinfo->state.feedback_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.feedback_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.fp2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_horz_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_panel_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_vert_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.gen_int_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.grph2_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.grph_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.htotal_cntl2 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.i2c_cntl_1 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.lvds_pll_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.mpp_gp_config | 0-u32max |
| HOST_DATA | 0 | rinfo->state.mpp_tb_config | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ov0_scale_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_clr | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_wid_left_right | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_wid_top_bottom | 0-u32max |
| HOST_DATA | 0 | rinfo->state.p2pll_div_0 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.p2pll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->state.palette_valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.post_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.post_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.ppll_div_3 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ppll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->state.rbbm_soft_reset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.subpic_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.surface_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.tmds_crc | 0-u32max |
| HOST_DATA | 0 | rinfo->state.tmds_transmitter_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.vclk_ecp_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.viph_control | 0-u32max |
| UNITS | 0 | rinfo | unit_byte |
| HALF_LOCKED2 | global &console_sem |
drivers/video/fbdev/aty/radeon_pm.c radeon_pm_disable_dynamic_mode() -> _radeon_msleep()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | rinfo | 4096-ptr_max |
| PARAM_VALUE | 0 | rinfo->dp_gui_master_cntl | 268435456,268435968-268436480,268436992 |
| PARAM_VALUE | 0 | rinfo->dynclk | (-1)-s32max |
| PARAM_VALUE | 0 | rinfo->family | 0-12,14-255 |
| PARAM_VALUE | 0 | rinfo->fp_bios_start | 0-u16max |
| PARAM_VALUE | 0 | rinfo->has_CRTC2 | s32min-(-1),1-s32max |
| PARAM_VALUE | 0 | rinfo->is_mobility | s32min-(-1),1-s32max |
| PARAM_VALUE | 0 | rinfo->lvds_timer.entry.pprev | 0 |
| PARAM_VALUE | 0 | rinfo->lvds_timer.flags | 0-4194302 |
| PARAM_VALUE | 0 | rinfo->panel_info.fbk_divider | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.hAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->panel_info.post_divider | 0-255 |
| PARAM_VALUE | 0 | rinfo->panel_info.pwr_delay | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.ref_divider | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.use_bios_dividers | 1 |
| PARAM_VALUE | 0 | rinfo->panel_info.vAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->panel_info.valid | 1 |
| PARAM_VALUE | 0 | rinfo->reinit_func | 74877280292859904 |
| PARAM_VALUE | 0 | rinfo->reversed_DAC | 0-s32max |
| PARAM_VALUE | 0 | rinfo->reversed_TMDS | 1 |
| PARAM_VALUE | 0 | rinfo->video_ram | 0,8388608,16777216-520093696 |
| PARAM_VALUE | 0 | rinfo->vram_ddr | 0-1 |
| PARAM_VALUE | 0 | rinfo->vram_width | 32,64,128,256 |
| PARAM_VALUE | 1 | ms | 16 |
| BUF_SIZE | 0 | rinfo | 2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| BUF_SIZE | 0 | rinfo | 2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| BUF_SIZE | 0 | rinfo->pdev | (-1),16,24,40,56,108-1096,1384,1600,1616,1752,2072,2576,7472,8064 |
| DATA_SOURCE | 0 | rinfo | $0 |
| FUZZY_MAX | 0 | rinfo->family | 3 |
| FUZZY_MAX | 0 | rinfo->has_CRTC2 | 1 |
| FUZZY_MAX | 0 | rinfo->is_mobility | 1 |
| STR_LEN | 0 | rinfo->name | (-1),49 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HOST_DATA | 0 | rinfo->fb_local_base | 0,65536-4294901760 |
| HOST_DATA | 0 | rinfo->fp_bios_start | 0-u16max |
| HOST_DATA | 0 | rinfo->init_state.amcgpio_en_reg | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.amcgpio_mask | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.bios_5_scratch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.bus_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.cap0_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.cap1_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.clk_cntl_index | 0,64-u32max |
| HOST_DATA | 0 | rinfo->init_state.clock_cntl_index | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_ext_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_more_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dac2_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dac_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp2_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_hw_debug | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_output_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dot_clock_freq | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dot_clock_freq_2 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dp_datatype | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.feedback_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.feedback_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_horz_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_panel_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_vert_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.gen_int_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.grph2_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.grph_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.htotal_cntl2 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.i2c_cntl_1 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.lvds_pll_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.mpp_gp_config | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.mpp_tb_config | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ov0_scale_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_clr | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_wid_left_right | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_wid_top_bottom | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.p2pll_div_0 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.p2pll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.palette_valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.post_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.post_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.ppll_div_3 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ppll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.rbbm_soft_reset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.subpic_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.surface_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.tmds_crc | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.tmds_transmitter_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.vclk_ecp_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.viph_control | 0-u32max |
| HOST_DATA | 0 | rinfo->panel_info->clock | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->fbk_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hAct_high | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hOver_plus | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hSync_width | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hblank | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->interlaced | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->post_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->pwr_delay | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->ref_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->use_bios_dividers | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vAct_high | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vOver_plus | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vSync_width | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vblank | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->xres | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->yres | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info.clock | 0-u16max |
| HOST_DATA | 0 | rinfo->panel_info.fbk_divider | 0-u16max |
| HOST_DATA | 0 | rinfo->panel_info.hOver_plus | 0-s16max[c] |
| HOST_DATA | 0 | rinfo->panel_info.hSync_width | 0-2040 |
| HOST_DATA | 0 | rinfo->panel_info.hblank | (-524280)-(-8),0-524280[c] |
| HOST_DATA | 0 | rinfo->panel_info.post_divider | 0-255 |
| HOST_DATA | 0 | rinfo->panel_info.vOver_plus | (-65535)-255 |
| HOST_DATA | 0 | rinfo->panel_info.vSync_width | 0[c] |
| HOST_DATA | 0 | rinfo->panel_info.vblank | (-65535)-u16max |
| HOST_DATA | 0 | rinfo->panel_info.xres | 9-4096[c] |
| HOST_DATA | 0 | rinfo->panel_info.yres | 0-u16max[c] |
| HOST_DATA | 0 | rinfo->pdev->current_state | 0-3[c] |
| HOST_DATA | 0 | rinfo->pending_lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->pll.ppll_max | s32min-s32max |
| HOST_DATA | 0 | rinfo->pll.ppll_min | s32min-s32max |
| HOST_DATA | 0 | rinfo->pll.ref_clk | 0-u16max |
| HOST_DATA | 0 | rinfo->pll.ref_div | 0-u16max |
| HOST_DATA | 0 | rinfo->state.amcgpio_en_reg | 0-u32max |
| HOST_DATA | 0 | rinfo->state.amcgpio_mask | 0-u32max |
| HOST_DATA | 0 | rinfo->state.bios_5_scratch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.bus_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.cap0_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.cap1_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.clk_cntl_index | 0,64-u32max |
| HOST_DATA | 0 | rinfo->state.clock_cntl_index | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_ext_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_more_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dac2_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dac_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp2_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_hw_debug | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_output_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dot_clock_freq | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dot_clock_freq_2 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dp_datatype | 0-u32max |
| HOST_DATA | 0 | rinfo->state.feedback_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.feedback_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.fp2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_horz_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_panel_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_vert_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.gen_int_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.grph2_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.grph_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.htotal_cntl2 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.i2c_cntl_1 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.lvds_pll_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.mpp_gp_config | 0-u32max |
| HOST_DATA | 0 | rinfo->state.mpp_tb_config | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ov0_scale_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_clr | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_wid_left_right | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_wid_top_bottom | 0-u32max |
| HOST_DATA | 0 | rinfo->state.p2pll_div_0 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.p2pll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->state.palette_valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.post_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.post_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.ppll_div_3 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ppll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->state.rbbm_soft_reset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.subpic_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.surface_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.tmds_crc | 0-u32max |
| HOST_DATA | 0 | rinfo->state.tmds_transmitter_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.vclk_ecp_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.viph_control | 0-u32max |
| UNITS | 0 | rinfo | unit_byte |
| HALF_LOCKED2 | global &console_sem |
drivers/video/fbdev/aty/radeon_pm.c radeon_pm_disable_dynamic_mode() -> _radeon_msleep()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | rinfo | 4096-ptr_max |
| PARAM_VALUE | 0 | rinfo->dp_gui_master_cntl | 268435456,268435968-268436480,268436992 |
| PARAM_VALUE | 0 | rinfo->dynclk | (-1)-s32max |
| PARAM_VALUE | 0 | rinfo->family | 0-12,14-255 |
| PARAM_VALUE | 0 | rinfo->fp_bios_start | 0-u16max |
| PARAM_VALUE | 0 | rinfo->has_CRTC2 | s32min-(-1),1-s32max |
| PARAM_VALUE | 0 | rinfo->lvds_timer.entry.pprev | 0 |
| PARAM_VALUE | 0 | rinfo->lvds_timer.flags | 0-4194302 |
| PARAM_VALUE | 0 | rinfo->panel_info.fbk_divider | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.hAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->panel_info.post_divider | 0-255 |
| PARAM_VALUE | 0 | rinfo->panel_info.pwr_delay | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.ref_divider | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.use_bios_dividers | 1 |
| PARAM_VALUE | 0 | rinfo->panel_info.vAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->panel_info.valid | 1 |
| PARAM_VALUE | 0 | rinfo->reinit_func | 74877280292859904 |
| PARAM_VALUE | 0 | rinfo->reversed_DAC | 0-s32max |
| PARAM_VALUE | 0 | rinfo->reversed_TMDS | 1 |
| PARAM_VALUE | 0 | rinfo->video_ram | 0,8388608,16777216-520093696 |
| PARAM_VALUE | 0 | rinfo->vram_ddr | 0-1 |
| PARAM_VALUE | 0 | rinfo->vram_width | 32,64,128,256 |
| PARAM_VALUE | 1 | ms | 16 |
| BUF_SIZE | 0 | rinfo | 2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| BUF_SIZE | 0 | rinfo | 2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| BUF_SIZE | 0 | rinfo->pdev | (-1),16,24,40,56,108-1096,1384,1600,1616,1752,2072,2576,7472,8064 |
| DATA_SOURCE | 0 | rinfo | $0 |
| FUZZY_MAX | 0 | rinfo->family | 3 |
| FUZZY_MAX | 0 | rinfo->has_CRTC2 | 1 |
| STR_LEN | 0 | rinfo->name | (-1),49 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HOST_DATA | 0 | rinfo->fb_local_base | 0,65536-4294901760 |
| HOST_DATA | 0 | rinfo->fp_bios_start | 0-u16max |
| HOST_DATA | 0 | rinfo->init_state.amcgpio_en_reg | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.amcgpio_mask | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.bios_5_scratch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.bus_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.cap0_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.cap1_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.clk_cntl_index | 0,64-u32max |
| HOST_DATA | 0 | rinfo->init_state.clock_cntl_index | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_ext_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_more_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dac2_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dac_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp2_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_hw_debug | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_output_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dot_clock_freq | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dot_clock_freq_2 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dp_datatype | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.feedback_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.feedback_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_horz_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_panel_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_vert_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.gen_int_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.grph2_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.grph_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.htotal_cntl2 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.i2c_cntl_1 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.lvds_pll_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.mpp_gp_config | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.mpp_tb_config | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ov0_scale_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_clr | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_wid_left_right | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_wid_top_bottom | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.p2pll_div_0 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.p2pll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.palette_valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.post_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.post_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.ppll_div_3 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ppll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.rbbm_soft_reset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.subpic_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.surface_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.tmds_crc | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.tmds_transmitter_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.vclk_ecp_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.viph_control | 0-u32max |
| HOST_DATA | 0 | rinfo->panel_info->clock | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->fbk_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hAct_high | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hOver_plus | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hSync_width | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hblank | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->interlaced | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->post_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->pwr_delay | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->ref_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->use_bios_dividers | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vAct_high | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vOver_plus | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vSync_width | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vblank | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->xres | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->yres | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info.clock | 0-u16max |
| HOST_DATA | 0 | rinfo->panel_info.fbk_divider | 0-u16max |
| HOST_DATA | 0 | rinfo->panel_info.hOver_plus | 0-s16max[c] |
| HOST_DATA | 0 | rinfo->panel_info.hSync_width | 0-2040 |
| HOST_DATA | 0 | rinfo->panel_info.hblank | (-524280)-(-8),0-524280[c] |
| HOST_DATA | 0 | rinfo->panel_info.post_divider | 0-255 |
| HOST_DATA | 0 | rinfo->panel_info.vOver_plus | (-65535)-255 |
| HOST_DATA | 0 | rinfo->panel_info.vSync_width | 0[c] |
| HOST_DATA | 0 | rinfo->panel_info.vblank | (-65535)-u16max |
| HOST_DATA | 0 | rinfo->panel_info.xres | 9-4096[c] |
| HOST_DATA | 0 | rinfo->panel_info.yres | 0-u16max[c] |
| HOST_DATA | 0 | rinfo->pdev->current_state | 0-3[c] |
| HOST_DATA | 0 | rinfo->pending_lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->pll.ppll_max | s32min-s32max |
| HOST_DATA | 0 | rinfo->pll.ppll_min | s32min-s32max |
| HOST_DATA | 0 | rinfo->pll.ref_clk | 0-u16max |
| HOST_DATA | 0 | rinfo->pll.ref_div | 0-u16max |
| HOST_DATA | 0 | rinfo->state.amcgpio_en_reg | 0-u32max |
| HOST_DATA | 0 | rinfo->state.amcgpio_mask | 0-u32max |
| HOST_DATA | 0 | rinfo->state.bios_5_scratch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.bus_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.cap0_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.cap1_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.clk_cntl_index | 0,64-u32max |
| HOST_DATA | 0 | rinfo->state.clock_cntl_index | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_ext_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_more_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dac2_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dac_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp2_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_hw_debug | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_output_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dot_clock_freq | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dot_clock_freq_2 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dp_datatype | 0-u32max |
| HOST_DATA | 0 | rinfo->state.feedback_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.feedback_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.fp2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_horz_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_panel_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_vert_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.gen_int_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.grph2_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.grph_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.htotal_cntl2 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.i2c_cntl_1 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.lvds_pll_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.mpp_gp_config | 0-u32max |
| HOST_DATA | 0 | rinfo->state.mpp_tb_config | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ov0_scale_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_clr | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_wid_left_right | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_wid_top_bottom | 0-u32max |
| HOST_DATA | 0 | rinfo->state.p2pll_div_0 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.p2pll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->state.palette_valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.post_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.post_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.ppll_div_3 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ppll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->state.rbbm_soft_reset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.subpic_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.surface_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.tmds_crc | 0-u32max |
| HOST_DATA | 0 | rinfo->state.tmds_transmitter_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.vclk_ecp_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.viph_control | 0-u32max |
| UNITS | 0 | rinfo | unit_byte |
| HALF_LOCKED2 | global &console_sem |
drivers/video/fbdev/aty/radeon_pm.c radeon_pm_disable_dynamic_mode() -> _radeon_msleep()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | rinfo | 4096-ptr_max |
| PARAM_VALUE | 0 | rinfo->dp_gui_master_cntl | 268435456,268435968-268436480,268436992 |
| PARAM_VALUE | 0 | rinfo->dynclk | (-1)-s32max |
| PARAM_VALUE | 0 | rinfo->family | 0-12,14-255 |
| PARAM_VALUE | 0 | rinfo->fp_bios_start | 0-u16max |
| PARAM_VALUE | 0 | rinfo->has_CRTC2 | s32min-(-1),1-s32max |
| PARAM_VALUE | 0 | rinfo->lvds_timer.entry.pprev | 0 |
| PARAM_VALUE | 0 | rinfo->lvds_timer.flags | 0-4194302 |
| PARAM_VALUE | 0 | rinfo->panel_info.fbk_divider | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.hAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->panel_info.post_divider | 0-255 |
| PARAM_VALUE | 0 | rinfo->panel_info.pwr_delay | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.ref_divider | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.use_bios_dividers | 1 |
| PARAM_VALUE | 0 | rinfo->panel_info.vAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->panel_info.valid | 1 |
| PARAM_VALUE | 0 | rinfo->reinit_func | 74877280292859904 |
| PARAM_VALUE | 0 | rinfo->reversed_DAC | 0-s32max |
| PARAM_VALUE | 0 | rinfo->reversed_TMDS | 1 |
| PARAM_VALUE | 0 | rinfo->video_ram | 0,8388608,16777216-520093696 |
| PARAM_VALUE | 0 | rinfo->vram_ddr | 0-1 |
| PARAM_VALUE | 0 | rinfo->vram_width | 32,64,128,256 |
| PARAM_VALUE | 1 | ms | 16 |
| BUF_SIZE | 0 | rinfo | 2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| BUF_SIZE | 0 | rinfo | 2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| BUF_SIZE | 0 | rinfo->pdev | (-1),16,24,40,56,108-1096,1384,1600,1616,1752,2072,2576,7472,8064 |
| DATA_SOURCE | 0 | rinfo | $0 |
| FUZZY_MAX | 0 | rinfo->family | 3 |
| FUZZY_MAX | 0 | rinfo->has_CRTC2 | 1 |
| STR_LEN | 0 | rinfo->name | (-1),49 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HOST_DATA | 0 | rinfo->fb_local_base | 0,65536-4294901760 |
| HOST_DATA | 0 | rinfo->fp_bios_start | 0-u16max |
| HOST_DATA | 0 | rinfo->init_state.amcgpio_en_reg | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.amcgpio_mask | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.bios_5_scratch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.bus_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.cap0_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.cap1_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.clk_cntl_index | 0,64-u32max |
| HOST_DATA | 0 | rinfo->init_state.clock_cntl_index | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_ext_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_more_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dac2_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dac_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp2_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_hw_debug | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_output_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dot_clock_freq | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dot_clock_freq_2 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dp_datatype | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.feedback_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.feedback_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_horz_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_panel_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_vert_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.gen_int_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.grph2_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.grph_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.htotal_cntl2 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.i2c_cntl_1 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.lvds_pll_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.mpp_gp_config | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.mpp_tb_config | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ov0_scale_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_clr | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_wid_left_right | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_wid_top_bottom | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.p2pll_div_0 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.p2pll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.palette_valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.post_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.post_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.ppll_div_3 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ppll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.rbbm_soft_reset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.subpic_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.surface_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.tmds_crc | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.tmds_transmitter_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.vclk_ecp_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.viph_control | 0-u32max |
| HOST_DATA | 0 | rinfo->panel_info->clock | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->fbk_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hAct_high | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hOver_plus | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hSync_width | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hblank | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->interlaced | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->post_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->pwr_delay | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->ref_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->use_bios_dividers | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vAct_high | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vOver_plus | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vSync_width | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vblank | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->xres | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->yres | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info.clock | 0-u16max |
| HOST_DATA | 0 | rinfo->panel_info.fbk_divider | 0-u16max |
| HOST_DATA | 0 | rinfo->panel_info.hOver_plus | 0-s16max[c] |
| HOST_DATA | 0 | rinfo->panel_info.hSync_width | 0-2040 |
| HOST_DATA | 0 | rinfo->panel_info.hblank | (-524280)-(-8),0-524280[c] |
| HOST_DATA | 0 | rinfo->panel_info.post_divider | 0-255 |
| HOST_DATA | 0 | rinfo->panel_info.vOver_plus | (-65535)-255 |
| HOST_DATA | 0 | rinfo->panel_info.vSync_width | 0[c] |
| HOST_DATA | 0 | rinfo->panel_info.vblank | (-65535)-u16max |
| HOST_DATA | 0 | rinfo->panel_info.xres | 9-4096[c] |
| HOST_DATA | 0 | rinfo->panel_info.yres | 0-u16max[c] |
| HOST_DATA | 0 | rinfo->pdev->current_state | 0-3[c] |
| HOST_DATA | 0 | rinfo->pending_lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->pll.ppll_max | s32min-s32max |
| HOST_DATA | 0 | rinfo->pll.ppll_min | s32min-s32max |
| HOST_DATA | 0 | rinfo->pll.ref_clk | 0-u16max |
| HOST_DATA | 0 | rinfo->pll.ref_div | 0-u16max |
| HOST_DATA | 0 | rinfo->state.amcgpio_en_reg | 0-u32max |
| HOST_DATA | 0 | rinfo->state.amcgpio_mask | 0-u32max |
| HOST_DATA | 0 | rinfo->state.bios_5_scratch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.bus_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.cap0_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.cap1_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.clk_cntl_index | 0,64-u32max |
| HOST_DATA | 0 | rinfo->state.clock_cntl_index | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_ext_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_more_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dac2_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dac_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp2_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_hw_debug | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_output_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dot_clock_freq | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dot_clock_freq_2 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dp_datatype | 0-u32max |
| HOST_DATA | 0 | rinfo->state.feedback_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.feedback_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.fp2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_horz_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_panel_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_vert_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.gen_int_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.grph2_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.grph_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.htotal_cntl2 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.i2c_cntl_1 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.lvds_pll_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.mpp_gp_config | 0-u32max |
| HOST_DATA | 0 | rinfo->state.mpp_tb_config | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ov0_scale_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_clr | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_wid_left_right | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_wid_top_bottom | 0-u32max |
| HOST_DATA | 0 | rinfo->state.p2pll_div_0 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.p2pll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->state.palette_valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.post_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.post_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.ppll_div_3 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ppll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->state.rbbm_soft_reset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.subpic_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.surface_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.tmds_crc | 0-u32max |
| HOST_DATA | 0 | rinfo->state.tmds_transmitter_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.vclk_ecp_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.viph_control | 0-u32max |
| UNITS | 0 | rinfo | unit_byte |
| HALF_LOCKED2 | global &console_sem |
drivers/video/fbdev/aty/radeon_pm.c radeon_pm_enable_dynamic_mode() -> _radeon_msleep()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | rinfo | 4096-ptr_max |
| PARAM_VALUE | 0 | rinfo->dp_gui_master_cntl | 268435456,268435968-268436480,268436992 |
| PARAM_VALUE | 0 | rinfo->dynclk | 1 |
| PARAM_VALUE | 0 | rinfo->family | 11-12 |
| PARAM_VALUE | 0 | rinfo->fp_bios_start | 0-u16max |
| PARAM_VALUE | 0 | rinfo->has_CRTC2 | s32min-(-1),1-s32max |
| PARAM_VALUE | 0 | rinfo->lvds_timer.entry.pprev | 0 |
| PARAM_VALUE | 0 | rinfo->lvds_timer.flags | 0-4194302 |
| PARAM_VALUE | 0 | rinfo->panel_info.fbk_divider | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.hAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->panel_info.post_divider | 0-255 |
| PARAM_VALUE | 0 | rinfo->panel_info.pwr_delay | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.ref_divider | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.use_bios_dividers | 1 |
| PARAM_VALUE | 0 | rinfo->panel_info.vAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->panel_info.valid | 1 |
| PARAM_VALUE | 0 | rinfo->reinit_func | 74877280292859904 |
| PARAM_VALUE | 0 | rinfo->reversed_DAC | 0-s32max |
| PARAM_VALUE | 0 | rinfo->reversed_TMDS | 1 |
| PARAM_VALUE | 0 | rinfo->video_ram | 0,8388608,16777216-520093696 |
| PARAM_VALUE | 0 | rinfo->vram_ddr | 0-1 |
| PARAM_VALUE | 0 | rinfo->vram_width | 32,64,128,256 |
| PARAM_VALUE | 1 | ms | 15 |
| BUF_SIZE | 0 | rinfo | 2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| BUF_SIZE | 0 | rinfo | 2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| BUF_SIZE | 0 | rinfo->pdev | (-1),16,24,40,56,108-1096,1384,1600,1616,1752,2072,2576,7472,8064 |
| DATA_SOURCE | 0 | rinfo | $0 |
| FUZZY_MAX | 0 | rinfo->has_CRTC2 | 1 |
| STR_LEN | 0 | rinfo->name | (-1),49 |
| BIT_INFO | 0 | rinfo->family | 0x8,0xf |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HOST_DATA | 0 | rinfo->fb_local_base | 0,65536-4294901760 |
| HOST_DATA | 0 | rinfo->fp_bios_start | 0-u16max |
| HOST_DATA | 0 | rinfo->init_state.amcgpio_en_reg | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.amcgpio_mask | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.bios_5_scratch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.bus_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.cap0_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.cap1_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.clk_cntl_index | 0,64-u32max |
| HOST_DATA | 0 | rinfo->init_state.clock_cntl_index | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_ext_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_more_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dac2_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dac_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp2_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_hw_debug | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_output_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dot_clock_freq | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dot_clock_freq_2 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dp_datatype | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.feedback_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.feedback_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_horz_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_panel_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_vert_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.gen_int_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.grph2_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.grph_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.htotal_cntl2 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.i2c_cntl_1 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.lvds_pll_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.mpp_gp_config | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.mpp_tb_config | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ov0_scale_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_clr | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_wid_left_right | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_wid_top_bottom | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.p2pll_div_0 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.p2pll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.palette_valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.post_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.post_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.ppll_div_3 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ppll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.rbbm_soft_reset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.subpic_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.surface_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.tmds_crc | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.tmds_transmitter_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.vclk_ecp_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.viph_control | 0-u32max |
| HOST_DATA | 0 | rinfo->panel_info->clock | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->fbk_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hAct_high | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hOver_plus | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hSync_width | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hblank | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->interlaced | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->post_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->pwr_delay | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->ref_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->use_bios_dividers | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vAct_high | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vOver_plus | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vSync_width | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vblank | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->xres | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->yres | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info.clock | 0-u16max |
| HOST_DATA | 0 | rinfo->panel_info.fbk_divider | 0-u16max |
| HOST_DATA | 0 | rinfo->panel_info.hOver_plus | 0-s16max[c] |
| HOST_DATA | 0 | rinfo->panel_info.hSync_width | 0-2040 |
| HOST_DATA | 0 | rinfo->panel_info.hblank | (-524280)-(-8),0-524280[c] |
| HOST_DATA | 0 | rinfo->panel_info.post_divider | 0-255 |
| HOST_DATA | 0 | rinfo->panel_info.vOver_plus | (-65535)-255 |
| HOST_DATA | 0 | rinfo->panel_info.vSync_width | 0[c] |
| HOST_DATA | 0 | rinfo->panel_info.vblank | (-65535)-u16max |
| HOST_DATA | 0 | rinfo->panel_info.xres | 9-4096[c] |
| HOST_DATA | 0 | rinfo->panel_info.yres | 0-u16max[c] |
| HOST_DATA | 0 | rinfo->pdev->current_state | 0-3[c] |
| HOST_DATA | 0 | rinfo->pending_lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->pll.ppll_max | s32min-s32max |
| HOST_DATA | 0 | rinfo->pll.ppll_min | s32min-s32max |
| HOST_DATA | 0 | rinfo->pll.ref_clk | 0-u16max |
| HOST_DATA | 0 | rinfo->pll.ref_div | 0-u16max |
| HOST_DATA | 0 | rinfo->state.amcgpio_en_reg | 0-u32max |
| HOST_DATA | 0 | rinfo->state.amcgpio_mask | 0-u32max |
| HOST_DATA | 0 | rinfo->state.bios_5_scratch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.bus_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.cap0_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.cap1_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.clk_cntl_index | 0,64-u32max |
| HOST_DATA | 0 | rinfo->state.clock_cntl_index | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_ext_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_more_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dac2_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dac_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp2_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_hw_debug | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_output_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dot_clock_freq | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dot_clock_freq_2 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dp_datatype | 0-u32max |
| HOST_DATA | 0 | rinfo->state.feedback_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.feedback_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.fp2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_horz_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_panel_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_vert_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.gen_int_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.grph2_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.grph_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.htotal_cntl2 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.i2c_cntl_1 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.lvds_pll_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.mpp_gp_config | 0-u32max |
| HOST_DATA | 0 | rinfo->state.mpp_tb_config | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ov0_scale_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_clr | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_wid_left_right | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_wid_top_bottom | 0-u32max |
| HOST_DATA | 0 | rinfo->state.p2pll_div_0 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.p2pll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->state.palette_valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.post_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.post_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.ppll_div_3 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ppll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->state.rbbm_soft_reset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.subpic_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.surface_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.tmds_crc | 0-u32max |
| HOST_DATA | 0 | rinfo->state.tmds_transmitter_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.vclk_ecp_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.viph_control | 0-u32max |
| UNITS | 0 | rinfo | unit_byte |
| HALF_LOCKED2 | global &console_sem |
drivers/video/fbdev/aty/radeon_pm.c radeon_pm_enable_dynamic_mode() -> _radeon_msleep()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | rinfo | 4096-ptr_max |
| PARAM_VALUE | 0 | rinfo->dp_gui_master_cntl | 268435456,268435968-268436480,268436992 |
| PARAM_VALUE | 0 | rinfo->dynclk | 1 |
| PARAM_VALUE | 0 | rinfo->family | 0-12,14-255 |
| PARAM_VALUE | 0 | rinfo->fp_bios_start | 0-u16max |
| PARAM_VALUE | 0 | rinfo->has_CRTC2 | s32min-(-1),1-s32max |
| PARAM_VALUE | 0 | rinfo->lvds_timer.entry.pprev | 0 |
| PARAM_VALUE | 0 | rinfo->lvds_timer.flags | 0-4194302 |
| PARAM_VALUE | 0 | rinfo->panel_info.fbk_divider | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.hAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->panel_info.post_divider | 0-255 |
| PARAM_VALUE | 0 | rinfo->panel_info.pwr_delay | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.ref_divider | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.use_bios_dividers | 1 |
| PARAM_VALUE | 0 | rinfo->panel_info.vAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->panel_info.valid | 1 |
| PARAM_VALUE | 0 | rinfo->reinit_func | 74877280292859904 |
| PARAM_VALUE | 0 | rinfo->reversed_DAC | 0-s32max |
| PARAM_VALUE | 0 | rinfo->reversed_TMDS | 1 |
| PARAM_VALUE | 0 | rinfo->video_ram | 0,8388608,16777216-520093696 |
| PARAM_VALUE | 0 | rinfo->vram_ddr | 0-1 |
| PARAM_VALUE | 0 | rinfo->vram_width | 32,64,128,256 |
| PARAM_VALUE | 1 | ms | 15 |
| BUF_SIZE | 0 | rinfo | 2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| BUF_SIZE | 0 | rinfo | 2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| BUF_SIZE | 0 | rinfo->pdev | (-1),16,24,40,56,108-1096,1384,1600,1616,1752,2072,2576,7472,8064 |
| DATA_SOURCE | 0 | rinfo | $0 |
| FUZZY_MAX | 0 | rinfo->has_CRTC2 | 1 |
| STR_LEN | 0 | rinfo->name | (-1),49 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HOST_DATA | 0 | rinfo->fb_local_base | 0,65536-4294901760 |
| HOST_DATA | 0 | rinfo->fp_bios_start | 0-u16max |
| HOST_DATA | 0 | rinfo->init_state.amcgpio_en_reg | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.amcgpio_mask | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.bios_5_scratch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.bus_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.cap0_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.cap1_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.clk_cntl_index | 0,64-u32max |
| HOST_DATA | 0 | rinfo->init_state.clock_cntl_index | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_ext_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_more_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dac2_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dac_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp2_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_hw_debug | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_output_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dot_clock_freq | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dot_clock_freq_2 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dp_datatype | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.feedback_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.feedback_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_horz_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_panel_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_vert_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.gen_int_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.grph2_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.grph_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.htotal_cntl2 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.i2c_cntl_1 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.lvds_pll_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.mpp_gp_config | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.mpp_tb_config | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ov0_scale_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_clr | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_wid_left_right | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_wid_top_bottom | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.p2pll_div_0 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.p2pll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.palette_valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.post_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.post_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.ppll_div_3 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ppll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.rbbm_soft_reset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.subpic_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.surface_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.tmds_crc | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.tmds_transmitter_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.vclk_ecp_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.viph_control | 0-u32max |
| HOST_DATA | 0 | rinfo->panel_info->clock | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->fbk_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hAct_high | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hOver_plus | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hSync_width | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hblank | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->interlaced | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->post_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->pwr_delay | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->ref_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->use_bios_dividers | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vAct_high | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vOver_plus | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vSync_width | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vblank | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->xres | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->yres | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info.clock | 0-u16max |
| HOST_DATA | 0 | rinfo->panel_info.fbk_divider | 0-u16max |
| HOST_DATA | 0 | rinfo->panel_info.hOver_plus | 0-s16max[c] |
| HOST_DATA | 0 | rinfo->panel_info.hSync_width | 0-2040 |
| HOST_DATA | 0 | rinfo->panel_info.hblank | (-524280)-(-8),0-524280[c] |
| HOST_DATA | 0 | rinfo->panel_info.post_divider | 0-255 |
| HOST_DATA | 0 | rinfo->panel_info.vOver_plus | (-65535)-255 |
| HOST_DATA | 0 | rinfo->panel_info.vSync_width | 0[c] |
| HOST_DATA | 0 | rinfo->panel_info.vblank | (-65535)-u16max |
| HOST_DATA | 0 | rinfo->panel_info.xres | 9-4096[c] |
| HOST_DATA | 0 | rinfo->panel_info.yres | 0-u16max[c] |
| HOST_DATA | 0 | rinfo->pdev->current_state | 0-3[c] |
| HOST_DATA | 0 | rinfo->pending_lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->pll.ppll_max | s32min-s32max |
| HOST_DATA | 0 | rinfo->pll.ppll_min | s32min-s32max |
| HOST_DATA | 0 | rinfo->pll.ref_clk | 0-u16max |
| HOST_DATA | 0 | rinfo->pll.ref_div | 0-u16max |
| HOST_DATA | 0 | rinfo->state.amcgpio_en_reg | 0-u32max |
| HOST_DATA | 0 | rinfo->state.amcgpio_mask | 0-u32max |
| HOST_DATA | 0 | rinfo->state.bios_5_scratch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.bus_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.cap0_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.cap1_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.clk_cntl_index | 0,64-u32max |
| HOST_DATA | 0 | rinfo->state.clock_cntl_index | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_ext_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_more_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dac2_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dac_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp2_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_hw_debug | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_output_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dot_clock_freq | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dot_clock_freq_2 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dp_datatype | 0-u32max |
| HOST_DATA | 0 | rinfo->state.feedback_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.feedback_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.fp2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_horz_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_panel_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_vert_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.gen_int_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.grph2_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.grph_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.htotal_cntl2 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.i2c_cntl_1 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.lvds_pll_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.mpp_gp_config | 0-u32max |
| HOST_DATA | 0 | rinfo->state.mpp_tb_config | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ov0_scale_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_clr | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_wid_left_right | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_wid_top_bottom | 0-u32max |
| HOST_DATA | 0 | rinfo->state.p2pll_div_0 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.p2pll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->state.palette_valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.post_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.post_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.ppll_div_3 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ppll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->state.rbbm_soft_reset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.subpic_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.surface_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.tmds_crc | 0-u32max |
| HOST_DATA | 0 | rinfo->state.tmds_transmitter_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.vclk_ecp_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.viph_control | 0-u32max |
| UNITS | 0 | rinfo | unit_byte |
| HALF_LOCKED2 | global &console_sem |
drivers/video/fbdev/aty/radeon_pm.c radeon_pm_enable_dynamic_mode() -> _radeon_msleep()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | rinfo | 4096-ptr_max |
| PARAM_VALUE | 0 | rinfo->dp_gui_master_cntl | 268435456,268435968-268436480,268436992 |
| PARAM_VALUE | 0 | rinfo->dynclk | 1 |
| PARAM_VALUE | 0 | rinfo->family | 0-12,14-255 |
| PARAM_VALUE | 0 | rinfo->fp_bios_start | 0-u16max |
| PARAM_VALUE | 0 | rinfo->has_CRTC2 | s32min-(-1),1-s32max |
| PARAM_VALUE | 0 | rinfo->lvds_timer.entry.pprev | 0 |
| PARAM_VALUE | 0 | rinfo->lvds_timer.flags | 0-4194302 |
| PARAM_VALUE | 0 | rinfo->panel_info.fbk_divider | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.hAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->panel_info.post_divider | 0-255 |
| PARAM_VALUE | 0 | rinfo->panel_info.pwr_delay | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.ref_divider | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.use_bios_dividers | 1 |
| PARAM_VALUE | 0 | rinfo->panel_info.vAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->panel_info.valid | 1 |
| PARAM_VALUE | 0 | rinfo->reinit_func | 74877280292859904 |
| PARAM_VALUE | 0 | rinfo->reversed_DAC | 0-s32max |
| PARAM_VALUE | 0 | rinfo->reversed_TMDS | 1 |
| PARAM_VALUE | 0 | rinfo->video_ram | 0,8388608,16777216-520093696 |
| PARAM_VALUE | 0 | rinfo->vram_ddr | 0-1 |
| PARAM_VALUE | 0 | rinfo->vram_width | 32,64,128,256 |
| PARAM_VALUE | 1 | ms | 15 |
| BUF_SIZE | 0 | rinfo | 2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| BUF_SIZE | 0 | rinfo | 2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| BUF_SIZE | 0 | rinfo->pdev | (-1),16,24,40,56,108-1096,1384,1600,1616,1752,2072,2576,7472,8064 |
| DATA_SOURCE | 0 | rinfo | $0 |
| FUZZY_MAX | 0 | rinfo->has_CRTC2 | 1 |
| STR_LEN | 0 | rinfo->name | (-1),49 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HOST_DATA | 0 | rinfo->fb_local_base | 0,65536-4294901760 |
| HOST_DATA | 0 | rinfo->fp_bios_start | 0-u16max |
| HOST_DATA | 0 | rinfo->init_state.amcgpio_en_reg | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.amcgpio_mask | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.bios_5_scratch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.bus_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.cap0_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.cap1_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.clk_cntl_index | 0,64-u32max |
| HOST_DATA | 0 | rinfo->init_state.clock_cntl_index | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_ext_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_more_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dac2_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dac_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp2_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_hw_debug | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_output_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dot_clock_freq | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dot_clock_freq_2 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dp_datatype | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.feedback_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.feedback_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_horz_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_panel_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_vert_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.gen_int_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.grph2_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.grph_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.htotal_cntl2 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.i2c_cntl_1 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.lvds_pll_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.mpp_gp_config | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.mpp_tb_config | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ov0_scale_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_clr | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_wid_left_right | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_wid_top_bottom | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.p2pll_div_0 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.p2pll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.palette_valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.post_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.post_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.ppll_div_3 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ppll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.rbbm_soft_reset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.subpic_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.surface_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.tmds_crc | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.tmds_transmitter_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.vclk_ecp_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.viph_control | 0-u32max |
| HOST_DATA | 0 | rinfo->panel_info->clock | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->fbk_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hAct_high | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hOver_plus | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hSync_width | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hblank | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->interlaced | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->post_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->pwr_delay | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->ref_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->use_bios_dividers | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vAct_high | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vOver_plus | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vSync_width | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vblank | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->xres | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->yres | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info.clock | 0-u16max |
| HOST_DATA | 0 | rinfo->panel_info.fbk_divider | 0-u16max |
| HOST_DATA | 0 | rinfo->panel_info.hOver_plus | 0-s16max[c] |
| HOST_DATA | 0 | rinfo->panel_info.hSync_width | 0-2040 |
| HOST_DATA | 0 | rinfo->panel_info.hblank | (-524280)-(-8),0-524280[c] |
| HOST_DATA | 0 | rinfo->panel_info.post_divider | 0-255 |
| HOST_DATA | 0 | rinfo->panel_info.vOver_plus | (-65535)-255 |
| HOST_DATA | 0 | rinfo->panel_info.vSync_width | 0[c] |
| HOST_DATA | 0 | rinfo->panel_info.vblank | (-65535)-u16max |
| HOST_DATA | 0 | rinfo->panel_info.xres | 9-4096[c] |
| HOST_DATA | 0 | rinfo->panel_info.yres | 0-u16max[c] |
| HOST_DATA | 0 | rinfo->pdev->current_state | 0-3[c] |
| HOST_DATA | 0 | rinfo->pending_lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->pll.ppll_max | s32min-s32max |
| HOST_DATA | 0 | rinfo->pll.ppll_min | s32min-s32max |
| HOST_DATA | 0 | rinfo->pll.ref_clk | 0-u16max |
| HOST_DATA | 0 | rinfo->pll.ref_div | 0-u16max |
| HOST_DATA | 0 | rinfo->state.amcgpio_en_reg | 0-u32max |
| HOST_DATA | 0 | rinfo->state.amcgpio_mask | 0-u32max |
| HOST_DATA | 0 | rinfo->state.bios_5_scratch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.bus_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.cap0_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.cap1_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.clk_cntl_index | 0,64-u32max |
| HOST_DATA | 0 | rinfo->state.clock_cntl_index | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_ext_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_more_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dac2_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dac_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp2_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_hw_debug | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_output_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dot_clock_freq | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dot_clock_freq_2 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dp_datatype | 0-u32max |
| HOST_DATA | 0 | rinfo->state.feedback_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.feedback_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.fp2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_horz_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_panel_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_vert_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.gen_int_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.grph2_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.grph_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.htotal_cntl2 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.i2c_cntl_1 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.lvds_pll_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.mpp_gp_config | 0-u32max |
| HOST_DATA | 0 | rinfo->state.mpp_tb_config | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ov0_scale_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_clr | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_wid_left_right | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_wid_top_bottom | 0-u32max |
| HOST_DATA | 0 | rinfo->state.p2pll_div_0 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.p2pll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->state.palette_valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.post_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.post_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.ppll_div_3 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ppll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->state.rbbm_soft_reset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.subpic_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.surface_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.tmds_crc | 0-u32max |
| HOST_DATA | 0 | rinfo->state.tmds_transmitter_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.vclk_ecp_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.viph_control | 0-u32max |
| UNITS | 0 | rinfo | unit_byte |
| HALF_LOCKED2 | global &console_sem |
drivers/video/fbdev/aty/radeon_pm.c radeon_pm_enable_dynamic_mode() -> _radeon_msleep()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | rinfo | 4096-ptr_max |
| PARAM_VALUE | 0 | rinfo->dp_gui_master_cntl | 268435456,268435968-268436480,268436992 |
| PARAM_VALUE | 0 | rinfo->dynclk | 1 |
| PARAM_VALUE | 0 | rinfo->family | 0-12,14-255 |
| PARAM_VALUE | 0 | rinfo->fp_bios_start | 0-u16max |
| PARAM_VALUE | 0 | rinfo->has_CRTC2 | s32min-(-1),1-s32max |
| PARAM_VALUE | 0 | rinfo->lvds_timer.entry.pprev | 0 |
| PARAM_VALUE | 0 | rinfo->lvds_timer.flags | 0-4194302 |
| PARAM_VALUE | 0 | rinfo->panel_info.fbk_divider | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.hAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->panel_info.post_divider | 0-255 |
| PARAM_VALUE | 0 | rinfo->panel_info.pwr_delay | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.ref_divider | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.use_bios_dividers | 1 |
| PARAM_VALUE | 0 | rinfo->panel_info.vAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->panel_info.valid | 1 |
| PARAM_VALUE | 0 | rinfo->reinit_func | 74877280292859904 |
| PARAM_VALUE | 0 | rinfo->reversed_DAC | 0-s32max |
| PARAM_VALUE | 0 | rinfo->reversed_TMDS | 1 |
| PARAM_VALUE | 0 | rinfo->video_ram | 0,8388608,16777216-520093696 |
| PARAM_VALUE | 0 | rinfo->vram_ddr | 0-1 |
| PARAM_VALUE | 0 | rinfo->vram_width | 32,64,128,256 |
| PARAM_VALUE | 1 | ms | 15 |
| BUF_SIZE | 0 | rinfo | 2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| BUF_SIZE | 0 | rinfo | 2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| BUF_SIZE | 0 | rinfo->pdev | (-1),16,24,40,56,108-1096,1384,1600,1616,1752,2072,2576,7472,8064 |
| DATA_SOURCE | 0 | rinfo | $0 |
| FUZZY_MAX | 0 | rinfo->has_CRTC2 | 1 |
| STR_LEN | 0 | rinfo->name | (-1),49 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HOST_DATA | 0 | rinfo->fb_local_base | 0,65536-4294901760 |
| HOST_DATA | 0 | rinfo->fp_bios_start | 0-u16max |
| HOST_DATA | 0 | rinfo->init_state.amcgpio_en_reg | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.amcgpio_mask | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.bios_5_scratch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.bus_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.cap0_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.cap1_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.clk_cntl_index | 0,64-u32max |
| HOST_DATA | 0 | rinfo->init_state.clock_cntl_index | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_ext_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_more_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dac2_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dac_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp2_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_hw_debug | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_output_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dot_clock_freq | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dot_clock_freq_2 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dp_datatype | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.feedback_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.feedback_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_horz_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_panel_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_vert_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.gen_int_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.grph2_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.grph_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.htotal_cntl2 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.i2c_cntl_1 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.lvds_pll_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.mpp_gp_config | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.mpp_tb_config | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ov0_scale_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_clr | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_wid_left_right | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_wid_top_bottom | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.p2pll_div_0 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.p2pll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.palette_valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.post_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.post_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.ppll_div_3 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ppll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.rbbm_soft_reset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.subpic_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.surface_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.tmds_crc | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.tmds_transmitter_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.vclk_ecp_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.viph_control | 0-u32max |
| HOST_DATA | 0 | rinfo->panel_info->clock | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->fbk_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hAct_high | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hOver_plus | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hSync_width | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hblank | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->interlaced | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->post_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->pwr_delay | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->ref_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->use_bios_dividers | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vAct_high | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vOver_plus | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vSync_width | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vblank | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->xres | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->yres | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info.clock | 0-u16max |
| HOST_DATA | 0 | rinfo->panel_info.fbk_divider | 0-u16max |
| HOST_DATA | 0 | rinfo->panel_info.hOver_plus | 0-s16max[c] |
| HOST_DATA | 0 | rinfo->panel_info.hSync_width | 0-2040 |
| HOST_DATA | 0 | rinfo->panel_info.hblank | (-524280)-(-8),0-524280[c] |
| HOST_DATA | 0 | rinfo->panel_info.post_divider | 0-255 |
| HOST_DATA | 0 | rinfo->panel_info.vOver_plus | (-65535)-255 |
| HOST_DATA | 0 | rinfo->panel_info.vSync_width | 0[c] |
| HOST_DATA | 0 | rinfo->panel_info.vblank | (-65535)-u16max |
| HOST_DATA | 0 | rinfo->panel_info.xres | 9-4096[c] |
| HOST_DATA | 0 | rinfo->panel_info.yres | 0-u16max[c] |
| HOST_DATA | 0 | rinfo->pdev->current_state | 0-3[c] |
| HOST_DATA | 0 | rinfo->pending_lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->pll.ppll_max | s32min-s32max |
| HOST_DATA | 0 | rinfo->pll.ppll_min | s32min-s32max |
| HOST_DATA | 0 | rinfo->pll.ref_clk | 0-u16max |
| HOST_DATA | 0 | rinfo->pll.ref_div | 0-u16max |
| HOST_DATA | 0 | rinfo->state.amcgpio_en_reg | 0-u32max |
| HOST_DATA | 0 | rinfo->state.amcgpio_mask | 0-u32max |
| HOST_DATA | 0 | rinfo->state.bios_5_scratch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.bus_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.cap0_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.cap1_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.clk_cntl_index | 0,64-u32max |
| HOST_DATA | 0 | rinfo->state.clock_cntl_index | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_ext_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_more_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dac2_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dac_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp2_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_hw_debug | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_output_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dot_clock_freq | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dot_clock_freq_2 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dp_datatype | 0-u32max |
| HOST_DATA | 0 | rinfo->state.feedback_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.feedback_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.fp2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_horz_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_panel_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_vert_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.gen_int_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.grph2_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.grph_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.htotal_cntl2 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.i2c_cntl_1 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.lvds_pll_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.mpp_gp_config | 0-u32max |
| HOST_DATA | 0 | rinfo->state.mpp_tb_config | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ov0_scale_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_clr | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_wid_left_right | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_wid_top_bottom | 0-u32max |
| HOST_DATA | 0 | rinfo->state.p2pll_div_0 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.p2pll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->state.palette_valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.post_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.post_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.ppll_div_3 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ppll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->state.rbbm_soft_reset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.subpic_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.surface_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.tmds_crc | 0-u32max |
| HOST_DATA | 0 | rinfo->state.tmds_transmitter_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.vclk_ecp_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.viph_control | 0-u32max |
| UNITS | 0 | rinfo | unit_byte |
| HALF_LOCKED2 | global &console_sem |
drivers/video/fbdev/aty/radeon_pm.c radeon_pm_enable_dynamic_mode() -> _radeon_msleep()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | rinfo | 4096-ptr_max |
| PARAM_VALUE | 0 | rinfo->dp_gui_master_cntl | 268435456,268435968-268436480,268436992 |
| PARAM_VALUE | 0 | rinfo->dynclk | 1 |
| PARAM_VALUE | 0 | rinfo->family | 5,8,10 |
| PARAM_VALUE | 0 | rinfo->fp_bios_start | 0-u16max |
| PARAM_VALUE | 0 | rinfo->has_CRTC2 | s32min-(-1),1-s32max |
| PARAM_VALUE | 0 | rinfo->lvds_timer.entry.pprev | 0 |
| PARAM_VALUE | 0 | rinfo->lvds_timer.flags | 0-4194302 |
| PARAM_VALUE | 0 | rinfo->panel_info.fbk_divider | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.hAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->panel_info.post_divider | 0-255 |
| PARAM_VALUE | 0 | rinfo->panel_info.pwr_delay | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.ref_divider | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.use_bios_dividers | 1 |
| PARAM_VALUE | 0 | rinfo->panel_info.vAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->panel_info.valid | 1 |
| PARAM_VALUE | 0 | rinfo->reinit_func | 74877280292859904 |
| PARAM_VALUE | 0 | rinfo->reversed_DAC | 0-s32max |
| PARAM_VALUE | 0 | rinfo->reversed_TMDS | 1 |
| PARAM_VALUE | 0 | rinfo->video_ram | 0,8388608,16777216-520093696 |
| PARAM_VALUE | 0 | rinfo->vram_ddr | 0-1 |
| PARAM_VALUE | 0 | rinfo->vram_width | 32,64,128,256 |
| PARAM_VALUE | 1 | ms | 15 |
| BUF_SIZE | 0 | rinfo | 2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| BUF_SIZE | 0 | rinfo | 2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| BUF_SIZE | 0 | rinfo->pdev | (-1),16,24,40,56,108-1096,1384,1600,1616,1752,2072,2576,7472,8064 |
| DATA_SOURCE | 0 | rinfo | $0 |
| FUZZY_MAX | 0 | rinfo->has_CRTC2 | 1 |
| STR_LEN | 0 | rinfo->name | (-1),49 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HOST_DATA | 0 | rinfo->fb_local_base | 0,65536-4294901760 |
| HOST_DATA | 0 | rinfo->fp_bios_start | 0-u16max |
| HOST_DATA | 0 | rinfo->init_state.amcgpio_en_reg | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.amcgpio_mask | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.bios_5_scratch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.bus_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.cap0_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.cap1_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.clk_cntl_index | 0,64-u32max |
| HOST_DATA | 0 | rinfo->init_state.clock_cntl_index | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_ext_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_more_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dac2_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dac_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp2_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_hw_debug | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_output_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dot_clock_freq | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dot_clock_freq_2 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dp_datatype | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.feedback_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.feedback_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_horz_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_panel_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_vert_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.gen_int_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.grph2_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.grph_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.htotal_cntl2 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.i2c_cntl_1 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.lvds_pll_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.mpp_gp_config | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.mpp_tb_config | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ov0_scale_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_clr | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_wid_left_right | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_wid_top_bottom | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.p2pll_div_0 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.p2pll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.palette_valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.post_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.post_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.ppll_div_3 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ppll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.rbbm_soft_reset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.subpic_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.surface_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.tmds_crc | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.tmds_transmitter_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.vclk_ecp_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.viph_control | 0-u32max |
| HOST_DATA | 0 | rinfo->panel_info->clock | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->fbk_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hAct_high | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hOver_plus | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hSync_width | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hblank | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->interlaced | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->post_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->pwr_delay | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->ref_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->use_bios_dividers | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vAct_high | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vOver_plus | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vSync_width | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vblank | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->xres | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->yres | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info.clock | 0-u16max |
| HOST_DATA | 0 | rinfo->panel_info.fbk_divider | 0-u16max |
| HOST_DATA | 0 | rinfo->panel_info.hOver_plus | 0-s16max[c] |
| HOST_DATA | 0 | rinfo->panel_info.hSync_width | 0-2040 |
| HOST_DATA | 0 | rinfo->panel_info.hblank | (-524280)-(-8),0-524280[c] |
| HOST_DATA | 0 | rinfo->panel_info.post_divider | 0-255 |
| HOST_DATA | 0 | rinfo->panel_info.vOver_plus | (-65535)-255 |
| HOST_DATA | 0 | rinfo->panel_info.vSync_width | 0[c] |
| HOST_DATA | 0 | rinfo->panel_info.vblank | (-65535)-u16max |
| HOST_DATA | 0 | rinfo->panel_info.xres | 9-4096[c] |
| HOST_DATA | 0 | rinfo->panel_info.yres | 0-u16max[c] |
| HOST_DATA | 0 | rinfo->pdev->current_state | 0-3[c] |
| HOST_DATA | 0 | rinfo->pending_lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->pll.ppll_max | s32min-s32max |
| HOST_DATA | 0 | rinfo->pll.ppll_min | s32min-s32max |
| HOST_DATA | 0 | rinfo->pll.ref_clk | 0-u16max |
| HOST_DATA | 0 | rinfo->pll.ref_div | 0-u16max |
| HOST_DATA | 0 | rinfo->state.amcgpio_en_reg | 0-u32max |
| HOST_DATA | 0 | rinfo->state.amcgpio_mask | 0-u32max |
| HOST_DATA | 0 | rinfo->state.bios_5_scratch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.bus_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.cap0_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.cap1_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.clk_cntl_index | 0,64-u32max |
| HOST_DATA | 0 | rinfo->state.clock_cntl_index | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_ext_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_more_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dac2_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dac_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp2_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_hw_debug | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_output_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dot_clock_freq | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dot_clock_freq_2 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dp_datatype | 0-u32max |
| HOST_DATA | 0 | rinfo->state.feedback_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.feedback_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.fp2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_horz_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_panel_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_vert_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.gen_int_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.grph2_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.grph_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.htotal_cntl2 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.i2c_cntl_1 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.lvds_pll_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.mpp_gp_config | 0-u32max |
| HOST_DATA | 0 | rinfo->state.mpp_tb_config | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ov0_scale_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_clr | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_wid_left_right | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_wid_top_bottom | 0-u32max |
| HOST_DATA | 0 | rinfo->state.p2pll_div_0 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.p2pll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->state.palette_valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.post_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.post_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.ppll_div_3 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ppll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->state.rbbm_soft_reset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.subpic_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.surface_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.tmds_crc | 0-u32max |
| HOST_DATA | 0 | rinfo->state.tmds_transmitter_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.vclk_ecp_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.viph_control | 0-u32max |
| UNITS | 0 | rinfo | unit_byte |
| HALF_LOCKED2 | global &console_sem |
drivers/video/fbdev/aty/radeon_pm.c radeon_pm_enable_dynamic_mode() -> _radeon_msleep()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | rinfo | 4096-ptr_max |
| PARAM_VALUE | 0 | rinfo->dp_gui_master_cntl | 268435456,268435968-268436480,268436992 |
| PARAM_VALUE | 0 | rinfo->dynclk | 1 |
| PARAM_VALUE | 0 | rinfo->family | 5,8 |
| PARAM_VALUE | 0 | rinfo->fp_bios_start | 0-u16max |
| PARAM_VALUE | 0 | rinfo->has_CRTC2 | s32min-(-1),1-s32max |
| PARAM_VALUE | 0 | rinfo->lvds_timer.entry.pprev | 0 |
| PARAM_VALUE | 0 | rinfo->lvds_timer.flags | 0-4194302 |
| PARAM_VALUE | 0 | rinfo->panel_info.fbk_divider | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.hAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->panel_info.post_divider | 0-255 |
| PARAM_VALUE | 0 | rinfo->panel_info.pwr_delay | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.ref_divider | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.use_bios_dividers | 1 |
| PARAM_VALUE | 0 | rinfo->panel_info.vAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->panel_info.valid | 1 |
| PARAM_VALUE | 0 | rinfo->reinit_func | 74877280292859904 |
| PARAM_VALUE | 0 | rinfo->reversed_DAC | 0-s32max |
| PARAM_VALUE | 0 | rinfo->reversed_TMDS | 1 |
| PARAM_VALUE | 0 | rinfo->video_ram | 0,8388608,16777216-520093696 |
| PARAM_VALUE | 0 | rinfo->vram_ddr | 0-1 |
| PARAM_VALUE | 0 | rinfo->vram_width | 32,64,128,256 |
| PARAM_VALUE | 1 | ms | 15 |
| BUF_SIZE | 0 | rinfo | 2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| BUF_SIZE | 0 | rinfo | 2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| BUF_SIZE | 0 | rinfo->pdev | (-1),16,24,40,56,108-1096,1384,1600,1616,1752,2072,2576,7472,8064 |
| DATA_SOURCE | 0 | rinfo | $0 |
| FUZZY_MAX | 0 | rinfo->has_CRTC2 | 1 |
| STR_LEN | 0 | rinfo->name | (-1),49 |
| BIT_INFO | 0 | rinfo->family | 0x0,0xd |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HOST_DATA | 0 | rinfo->fb_local_base | 0,65536-4294901760 |
| HOST_DATA | 0 | rinfo->fp_bios_start | 0-u16max |
| HOST_DATA | 0 | rinfo->init_state.amcgpio_en_reg | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.amcgpio_mask | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.bios_5_scratch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.bus_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.cap0_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.cap1_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.clk_cntl_index | 0,64-u32max |
| HOST_DATA | 0 | rinfo->init_state.clock_cntl_index | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_ext_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_more_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dac2_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dac_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp2_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_hw_debug | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_output_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dot_clock_freq | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dot_clock_freq_2 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dp_datatype | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.feedback_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.feedback_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_horz_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_panel_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_vert_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.gen_int_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.grph2_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.grph_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.htotal_cntl2 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.i2c_cntl_1 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.lvds_pll_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.mpp_gp_config | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.mpp_tb_config | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ov0_scale_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_clr | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_wid_left_right | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_wid_top_bottom | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.p2pll_div_0 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.p2pll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.palette_valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.post_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.post_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.ppll_div_3 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ppll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.rbbm_soft_reset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.subpic_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.surface_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.tmds_crc | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.tmds_transmitter_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.vclk_ecp_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.viph_control | 0-u32max |
| HOST_DATA | 0 | rinfo->panel_info->clock | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->fbk_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hAct_high | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hOver_plus | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hSync_width | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hblank | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->interlaced | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->post_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->pwr_delay | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->ref_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->use_bios_dividers | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vAct_high | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vOver_plus | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vSync_width | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vblank | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->xres | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->yres | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info.clock | 0-u16max |
| HOST_DATA | 0 | rinfo->panel_info.fbk_divider | 0-u16max |
| HOST_DATA | 0 | rinfo->panel_info.hOver_plus | 0-s16max[c] |
| HOST_DATA | 0 | rinfo->panel_info.hSync_width | 0-2040 |
| HOST_DATA | 0 | rinfo->panel_info.hblank | (-524280)-(-8),0-524280[c] |
| HOST_DATA | 0 | rinfo->panel_info.post_divider | 0-255 |
| HOST_DATA | 0 | rinfo->panel_info.vOver_plus | (-65535)-255 |
| HOST_DATA | 0 | rinfo->panel_info.vSync_width | 0[c] |
| HOST_DATA | 0 | rinfo->panel_info.vblank | (-65535)-u16max |
| HOST_DATA | 0 | rinfo->panel_info.xres | 9-4096[c] |
| HOST_DATA | 0 | rinfo->panel_info.yres | 0-u16max[c] |
| HOST_DATA | 0 | rinfo->pdev->current_state | 0-3[c] |
| HOST_DATA | 0 | rinfo->pending_lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->pll.ppll_max | s32min-s32max |
| HOST_DATA | 0 | rinfo->pll.ppll_min | s32min-s32max |
| HOST_DATA | 0 | rinfo->pll.ref_clk | 0-u16max |
| HOST_DATA | 0 | rinfo->pll.ref_div | 0-u16max |
| HOST_DATA | 0 | rinfo->state.amcgpio_en_reg | 0-u32max |
| HOST_DATA | 0 | rinfo->state.amcgpio_mask | 0-u32max |
| HOST_DATA | 0 | rinfo->state.bios_5_scratch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.bus_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.cap0_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.cap1_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.clk_cntl_index | 0,64-u32max |
| HOST_DATA | 0 | rinfo->state.clock_cntl_index | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_ext_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_more_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dac2_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dac_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp2_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_hw_debug | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_output_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dot_clock_freq | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dot_clock_freq_2 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dp_datatype | 0-u32max |
| HOST_DATA | 0 | rinfo->state.feedback_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.feedback_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.fp2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_horz_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_panel_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_vert_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.gen_int_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.grph2_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.grph_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.htotal_cntl2 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.i2c_cntl_1 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.lvds_pll_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.mpp_gp_config | 0-u32max |
| HOST_DATA | 0 | rinfo->state.mpp_tb_config | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ov0_scale_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_clr | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_wid_left_right | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_wid_top_bottom | 0-u32max |
| HOST_DATA | 0 | rinfo->state.p2pll_div_0 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.p2pll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->state.palette_valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.post_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.post_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.ppll_div_3 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ppll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->state.rbbm_soft_reset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.subpic_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.surface_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.tmds_crc | 0-u32max |
| HOST_DATA | 0 | rinfo->state.tmds_transmitter_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.vclk_ecp_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.viph_control | 0-u32max |
| UNITS | 0 | rinfo | unit_byte |
| HALF_LOCKED2 | global &console_sem |
drivers/video/fbdev/aty/radeon_pm.c radeon_pm_enable_dynamic_mode() -> _radeon_msleep()
| Type | Parameter | Key | Value |
|---|---|---|---|
| PARAM_VALUE | 0 | rinfo | 4096-ptr_max |
| PARAM_VALUE | 0 | rinfo->dp_gui_master_cntl | 268435456,268435968-268436480,268436992 |
| PARAM_VALUE | 0 | rinfo->dynclk | 1 |
| PARAM_VALUE | 0 | rinfo->family | 0-12,14-255 |
| PARAM_VALUE | 0 | rinfo->fp_bios_start | 0-u16max |
| PARAM_VALUE | 0 | rinfo->has_CRTC2 | s32min-(-1),1-s32max |
| PARAM_VALUE | 0 | rinfo->lvds_timer.entry.pprev | 0 |
| PARAM_VALUE | 0 | rinfo->lvds_timer.flags | 0-4194302 |
| PARAM_VALUE | 0 | rinfo->panel_info.fbk_divider | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.hAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->panel_info.post_divider | 0-255 |
| PARAM_VALUE | 0 | rinfo->panel_info.pwr_delay | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.ref_divider | 0-u16max |
| PARAM_VALUE | 0 | rinfo->panel_info.use_bios_dividers | 1 |
| PARAM_VALUE | 0 | rinfo->panel_info.vAct_high | 0-1 |
| PARAM_VALUE | 0 | rinfo->panel_info.valid | 1 |
| PARAM_VALUE | 0 | rinfo->reinit_func | 74877280292859904 |
| PARAM_VALUE | 0 | rinfo->reversed_DAC | 0-s32max |
| PARAM_VALUE | 0 | rinfo->reversed_TMDS | 1 |
| PARAM_VALUE | 0 | rinfo->video_ram | 0,8388608,16777216-520093696 |
| PARAM_VALUE | 0 | rinfo->vram_ddr | 0-1 |
| PARAM_VALUE | 0 | rinfo->vram_width | 32,64,128,256 |
| PARAM_VALUE | 1 | ms | 15 |
| BUF_SIZE | 0 | rinfo | 2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| BUF_SIZE | 0 | rinfo | 2,4,16,24,32,128,216,248,256,1288,1984,2560 |
| BUF_SIZE | 0 | rinfo->pdev | (-1),16,24,40,56,108-1096,1384,1600,1616,1752,2072,2576,7472,8064 |
| DATA_SOURCE | 0 | rinfo | $0 |
| FUZZY_MAX | 0 | rinfo->has_CRTC2 | 1 |
| STR_LEN | 0 | rinfo->name | (-1),49 |
| RX_PATH | |||
| TASK_NOT_RUNNING | |||
| NOCHECK_CALL | |||
| HOST_DATA | 0 | rinfo->fb_local_base | 0,65536-4294901760 |
| HOST_DATA | 0 | rinfo->fp_bios_start | 0-u16max |
| HOST_DATA | 0 | rinfo->init_state.amcgpio_en_reg | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.amcgpio_mask | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.bios_5_scratch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.bus_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.cap0_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.cap1_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.clk_cntl_index | 0,64-u32max |
| HOST_DATA | 0 | rinfo->init_state.clock_cntl_index | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc2_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_ext_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_more_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dac2_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dac_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp2_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_hw_debug | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.disp_output_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dot_clock_freq | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dot_clock_freq_2 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.dp_datatype | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.feedback_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.feedback_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_horz_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_panel_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.fp_vert_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.gen_int_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.grph2_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.grph_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.htotal_cntl2 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.i2c_cntl_1 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.lvds_pll_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.mpp_gp_config | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.mpp_tb_config | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ov0_scale_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_clr | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_wid_left_right | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ovr_wid_top_bottom | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.p2pll_div_0 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.p2pll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.palette_valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.post_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.post_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->init_state.ppll_div_3 | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.ppll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.rbbm_soft_reset | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.subpic_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.surface_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.tmds_crc | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.tmds_transmitter_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.vclk_ecp_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->init_state.viph_control | 0-u32max |
| HOST_DATA | 0 | rinfo->panel_info->clock | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->fbk_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hAct_high | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hOver_plus | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hSync_width | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->hblank | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->interlaced | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->post_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->pwr_delay | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->ref_divider | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->use_bios_dividers | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vAct_high | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vOver_plus | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vSync_width | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->vblank | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->xres | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info->yres | s32min-s32max |
| HOST_DATA | 0 | rinfo->panel_info.clock | 0-u16max |
| HOST_DATA | 0 | rinfo->panel_info.fbk_divider | 0-u16max |
| HOST_DATA | 0 | rinfo->panel_info.hOver_plus | 0-s16max[c] |
| HOST_DATA | 0 | rinfo->panel_info.hSync_width | 0-2040 |
| HOST_DATA | 0 | rinfo->panel_info.hblank | (-524280)-(-8),0-524280[c] |
| HOST_DATA | 0 | rinfo->panel_info.post_divider | 0-255 |
| HOST_DATA | 0 | rinfo->panel_info.vOver_plus | (-65535)-255 |
| HOST_DATA | 0 | rinfo->panel_info.vSync_width | 0[c] |
| HOST_DATA | 0 | rinfo->panel_info.vblank | (-65535)-u16max |
| HOST_DATA | 0 | rinfo->panel_info.xres | 9-4096[c] |
| HOST_DATA | 0 | rinfo->panel_info.yres | 0-u16max[c] |
| HOST_DATA | 0 | rinfo->pdev->current_state | 0-3[c] |
| HOST_DATA | 0 | rinfo->pending_lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->pll.ppll_max | s32min-s32max |
| HOST_DATA | 0 | rinfo->pll.ppll_min | s32min-s32max |
| HOST_DATA | 0 | rinfo->pll.ref_clk | 0-u16max |
| HOST_DATA | 0 | rinfo->pll.ref_div | 0-u16max |
| HOST_DATA | 0 | rinfo->state.amcgpio_en_reg | 0-u32max |
| HOST_DATA | 0 | rinfo->state.amcgpio_mask | 0-u32max |
| HOST_DATA | 0 | rinfo->state.bios_5_scratch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.bus_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.cap0_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.cap1_trig_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.clk_cntl_index | 0,64-u32max |
| HOST_DATA | 0 | rinfo->state.clock_cntl_index | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc2_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_ext_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_more_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_offset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_offset_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_pitch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dac2_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dac_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp2_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_hw_debug | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_merge_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.disp_output_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dot_clock_freq | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dot_clock_freq_2 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.dp_datatype | 0-u32max |
| HOST_DATA | 0 | rinfo->state.feedback_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.feedback_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.fp2_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp2_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp2_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_crtc_h_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_crtc_v_total_disp | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_h_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_horz_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_panel_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_v_sync_strt_wid | 0-u32max |
| HOST_DATA | 0 | rinfo->state.fp_vert_stretch | 0-u32max |
| HOST_DATA | 0 | rinfo->state.gen_int_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.grph2_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.grph_buffer_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.htotal_cntl2 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.i2c_cntl_1 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.lvds_gen_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.lvds_pll_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.mpp_gp_config | 0-u32max |
| HOST_DATA | 0 | rinfo->state.mpp_tb_config | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ov0_scale_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_clr | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_wid_left_right | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ovr_wid_top_bottom | 0-u32max |
| HOST_DATA | 0 | rinfo->state.p2pll_div_0 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.p2pll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->state.palette_valid | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.post_div | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.post_div_2 | s32min-s32max |
| HOST_DATA | 0 | rinfo->state.ppll_div_3 | 0-u32max |
| HOST_DATA | 0 | rinfo->state.ppll_ref_div | 0-u32max |
| HOST_DATA | 0 | rinfo->state.rbbm_soft_reset | 0-u32max |
| HOST_DATA | 0 | rinfo->state.subpic_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.surface_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.tmds_crc | 0-u32max |
| HOST_DATA | 0 | rinfo->state.tmds_transmitter_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.vclk_ecp_cntl | 0-u32max |
| HOST_DATA | 0 | rinfo->state.viph_control | 0-u32max |
| UNITS | 0 | rinfo | unit_byte |
| HALF_LOCKED2 | global &console_sem |