| PARAM_VALUE |
0 |
rtwdev |
4096-ptr_max |
| PARAM_VALUE |
0 |
rtwdev->chip |
4096-ptr_max |
| PARAM_VALUE |
0 |
rtwdev->chip->bss_clr_vld.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->c2h_counter_reg.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->dcfo_comp->mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->dig_regs |
4096-ptr_max |
| PARAM_VALUE |
0 |
rtwdev->chip->dig_regs->p0_lna_init.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->dig_regs->p0_p20_pagcugc_en.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->dig_regs->p0_rxb_init.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->dig_regs->p0_s20_pagcugc_en.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->dig_regs->p0_tia_init.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->dig_regs->p1_lna_init.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->dig_regs->p1_p20_pagcugc_en.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->dig_regs->p1_rxb_init.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->dig_regs->p1_s20_pagcugc_en.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->dig_regs->p1_tia_init.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->h2c_cctl_func_id |
2 |
| PARAM_VALUE |
0 |
rtwdev->chip->h2c_counter_reg.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->h2c_desc_size |
16,24 |
| PARAM_VALUE |
0 |
rtwdev->chip->mac_def->agg_limit.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->mac_def->bfee_ctrl.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->mac_def->muedca_ctrl.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->mac_def->narrow_bw_ru_dis.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->mac_def->ra_agg_limit.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->mac_def->txcnt_limit.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->mac_def->wow_ctrl.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->needed_fw_elms |
107426,487220,524085,671612724,1074032436,1074229012,1074229044 |
| PARAM_VALUE |
0 |
rtwdev->chip->page_regs->ch_page_ctrl |
5892,35332,46852 |
| PARAM_VALUE |
0 |
rtwdev->chip->page_regs->hci_fc_ctrl |
5888,35328,46848 |
| PARAM_VALUE |
0 |
rtwdev->chip->page_regs->pub_page_ctrl1 |
6032,35472,46992 |
| PARAM_VALUE |
0 |
rtwdev->chip->page_regs->pub_page_ctrl2 |
6036,35476,46996 |
| PARAM_VALUE |
0 |
rtwdev->chip->page_regs->pub_page_info1 |
6040,35480,47004 |
| PARAM_VALUE |
0 |
rtwdev->chip->page_regs->pub_page_info2 |
6044,35484,47008 |
| PARAM_VALUE |
0 |
rtwdev->chip->page_regs->pub_page_info3 |
6028,35468,46988 |
| PARAM_VALUE |
0 |
rtwdev->chip->page_regs->wp_page_ctrl1 |
6048,35488,47012 |
| PARAM_VALUE |
0 |
rtwdev->chip->page_regs->wp_page_ctrl2 |
6052,35492,47016 |
| PARAM_VALUE |
0 |
rtwdev->chip->page_regs->wp_page_info1 |
6056,35496,47020 |
| PARAM_VALUE |
0 |
rtwdev->chip->phy_def->cr_base |
65536 |
| PARAM_VALUE |
0 |
rtwdev->chip->phy_def->physt_bmp_eht |
252 |
| PARAM_VALUE |
0 |
rtwdev->chip->phy_def->physt_bmp_start |
1852 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->ampdu_miss.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->brk.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->brk_option.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->cca_spoofing.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->cck_brk.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->cck_cca.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->cck_sfd_gg.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->cck_sig_gg.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->cck_spoofing.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->cck_txen.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->cck_txon.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->enable_all_cnt.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->lsig_brk_l_th.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->lsig_brk_s_th.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->ofdm_cca.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->r1b_rr_sel.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->r1b_rx_rpt_rst.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->rst_all_cnt.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->rxl_err_parity.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->rxl_err_rate.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pmac_regs->search_fail.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->pwr_off_seq->addr |
2,5-7,16,36,113,128,130-131,136,145-146,198,420,672,674,752-753 |
| PARAM_VALUE |
0 |
rtwdev->chip->pwr_on_seq->addr |
2,5-7,16,36,113,128,130-131,136,145-146,198,420,672,674,752-753 |
| PARAM_VALUE |
0 |
rtwdev->chip->rfkill_get.mask |
0-4,7,15,17,32,63,128,240,255,511-512,992,1023,2044,3072,4032 |
| PARAM_VALUE |
0 |
rtwdev->chip->rfkill_init->mode.addr |
98,724,728,1774,17712,17716,17720,17724,17728,17732,17736,17740 |
| PARAM_VALUE |
0 |
rtwdev->chip->rfkill_init->mode.data |
0-3,7-8,15-16,18,24,26,30,38,42,52,64,75,96,128,131467,205831 |
| PARAM_VALUE |
0 |
rtwdev->chip->rfkill_init->mode.mask |
2-4,7-8,15-16,31-32,51,56,63-64,128,192,240,255-256,448,511-512 |
| PARAM_VALUE |
0 |
rtwdev->chip->rfkill_init->pinmux.addr |
98,724,728,1774,17712,17716,17720,17724,17728,17732,17736,17740 |
| PARAM_VALUE |
0 |
rtwdev->chip->rfkill_init->pinmux.data |
0-3,7-8,15-16,18,24,26,30,38,42,52,64,75,96,128,131467,205831 |
| PARAM_VALUE |
0 |
rtwdev->chip->rfkill_init->pinmux.mask |
2-4,7-8,15-16,31-32,51,56,63-64,128,192,240,255-256,448,511-512 |
| PARAM_VALUE |
0 |
rtwdev->chip->rrsr_cfgs->ref_rate.addr |
98,724,728,1774,17712,17716,17720,17724,17728,17732,17736,17740 |
| PARAM_VALUE |
0 |
rtwdev->chip->rrsr_cfgs->ref_rate.mask |
2-4,7-8,15-16,31-32,51,56,63-64,128,192,240,255-256,448,511-512 |
| PARAM_VALUE |
0 |
rtwdev->chip->rrsr_cfgs->rsc.addr |
98,724,728,1774,17712,17716,17720,17724,17728,17732,17736,17740 |
| PARAM_VALUE |
0 |
rtwdev->chip->rrsr_cfgs->rsc.mask |
2-4,7-8,15-16,31-32,51,56,63-64,128,192,240,255-256,448,511-512 |
| PARAM_VALUE |
0 |
rtwdev->hal.antenna_tx |
1-2 |
| PARAM_VALUE |
0 |
rtwdev->hci.ops->deinit |
4096-ptr_max |
| PARAM_VALUE |
0 |
rtwdev->hci.ops->read16 |
4096-ptr_max |
| PARAM_VALUE |
0 |
rtwdev->hci.ops->read32 |
4096-ptr_max |
| PARAM_VALUE |
0 |
rtwdev->hci.ops->read8 |
4096-ptr_max |
| PARAM_VALUE |
0 |
rtwdev->hci.ops->start |
4096-ptr_max |
| PARAM_VALUE |
0 |
rtwdev->hci.ops->stop |
4096-ptr_max |
| PARAM_VALUE |
0 |
rtwdev->hci.ops->write16 |
4096-ptr_max |
| PARAM_VALUE |
0 |
rtwdev->hci.ops->write32 |
4096-ptr_max |
| PARAM_VALUE |
0 |
rtwdev->hci.ops->write8 |
4096-ptr_max |
| PARAM_VALUE |
0 |
rtwdev->io->do_mdelay |
0,4096-ptr_max |
| PARAM_VALUE |
0 |
rtwdev->io->do_udelay |
0,4096-ptr_max |
| PARAM_VALUE |
0 |
rtwdev->io->pack |
0,4096-ptr_max |
| PARAM_VALUE |
0 |
rtwdev->io->phy_write32 |
4096-ptr_max |
| PARAM_VALUE |
0 |
rtwdev->io->unpack |
0,4096-ptr_max |
| PARAM_VALUE |
0 |
rtwdev->io->write32 |
4096-ptr_max |
| PARAM_VALUE |
0 |
rtwdev->io->write8 |
4096-ptr_max |
| PARAM_VALUE |
0 |
rtwdev->io->write_rf |
4096-ptr_max |
| PARAM_VALUE |
1 |
skb |
4096-ptr_max |
| PARAM_VALUE |
1 |
skb->data_len |
0 |
| BUF_SIZE |
1 |
skb |
(-1)-s32max |
| BUF_SIZE |
1 |
skb |
(-1)-s32max |
| DATA_SOURCE |
0 |
rtwdev |
$0 |
| DATA_SOURCE |
1 |
skb |
r rtw89_fw_h2c_alloc_skb_with_hdr |
| RX_PATH |
|
|
|
| TASK_NOT_RUNNING |
|
|
|
| NOCHECK_CALL |
|
|
|
| LOCK2 |
|
rcu_read |
|
| HALF_LOCKED2 |
|
&ar->conf_mutex |
|
| HALF_LOCKED2 |
|
&dev->mt76.mutex |
|
| HALF_LOCKED2 |
|
&file->lock |
|
| HALF_LOCKED2 |
|
&local->hw.wiphy->mtx |
|
| HALF_LOCKED2 |
|
&mvm->mutex |
|
| HALF_LOCKED2 |
|
&mvmsta->deflink.lq_sta.rs_drv.pers.lock |
|
| HALF_LOCKED2 |
|
&pool->lock |
|
| HALF_LOCKED2 |
|
&priv->sta_mutex |
|
| HALF_LOCKED2 |
|
&rtwdev->hw->wiphy->mtx |
|
| HALF_LOCKED2 |
|
&rtwdev->mutex |
|
| HALF_LOCKED2 |
|
bh |
|
| HALF_LOCKED2 |
|
global &rtnl_mutex |
|